OBSOLETE
1, 2, 4 MEG x 32
DRAM SODIMMs
SMALL-OUTLINE
DRAM MODULE
FEATURES
• JEDEC pinout in a 72-pin, small-outline, dual in-line
memory module (DIMM)
• 4MB (1 Meg x 32), 8MB (2 Meg x 32) and
16MB (4 Meg x 32)
• High-performance CMOS silicon-gate process
• Single +3.3V
±0.3V
power supply
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
(CBR) and HIDDEN; optional self refresh (S)
• 1,024-cycle refresh distributed across 16ms (4MB and
8MB) or 2,048-cycle refresh distributed across 32ms
(16MB) or self refresh distributed across 128ms
• FAST PAGE MODE (FPM) or Extended Data-Out
(EDO) PAGE MODE access cycles
MT2LDT132H(X)(S), MT4LDT232H(X)(S),
MT8LDT432H(X)(S)
For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/mti/msp/html/datasheet.html
PIN ASSIGNMENT (Front View)
72-Pin Small-Outline DIMM
1
PIN
FRONT
PIN
1
V
SS
2
3
DQ1
4
5
DQ3
6
7
DQ5
8
9
DQ7
10
11
PRD1
12
13
A1
14
15
A3
16
17
A5
18
19
A10
20
21
DQ8
22
23
DQ10
24
25
DQ12
26
27
DQ14
28
29
NC (A11)
30
31
A8
32
33 NC/RAS3#** 34
35
DQ15
36
**8MB version only
NOTE:
Symbols in parentheses are not used on these modules but may be used
for other modules in this product family. They are for reference only.
BACK
DQ0
DQ2
DQ4
DQ6
V
DD
A0
A2
A4
A6
NC
DQ9
DQ11
DQ13
A7
V
DD
A9
RAS2#
NC
PIN
FRONT
PIN
37
DQ16
38
39
V
SS
40
41
CAS2#
42
43
CAS1#
44
45 NC/RAS1#** 46
47
WE#
48
49
DQ18
50
51
DQ20
52
53
DQ22
54
55
NC
56
57
DQ25
58
59
DQ28
60
61
V
DD
62
63
DQ30
64
65
NC
66
67
PRD3
68
69
PRD5
70
71
PRD7
72
BACK
DQ17
CAS0#
CAS3#
RAS0#
NC (A12)
NC (A13)
DQ19
DQ21
DQ23
DQ24
DQ26
DQ27
DQ29
DQ31
PRD2
PRD4
PRD6
V
SS
OPTIONS
• Package
72 -pin Small-Outline DIMM (gold)
• Timing
50ns access
60ns access
• Access Cycles
FAST PAGE MODE
EDO PAGE MODE
• Refresh Rates
Standard Refresh
Self Refresh (128ms period)
*EDO version only
MARKING
G
-5*
-6
None
X
None
S
KEY TIMING PARAMETERS
EDO Operating Mode (4MB and 8MB DIMMs)
SPEED
-5
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
84ns
104ns
50ns
60ns
20ns
25ns
25ns
30ns
15ns
15ns
8ns
10ns
FPM Operating Mode
SPEED
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
RP
EDO Operating Mode (16MB DIMM)
SPEED
-5
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
110ns
60ns
35ns
30ns
15ns
40ns
84ns
104ns
50ns
60ns
20ns
25ns
25ns
30ns
13ns
15ns
8ns
10ns
1, 2, 4 Meg x 32 DRAM SODIMMs
DM34.p65 – Rev. 6/98
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998,
Micron Technology, Inc.
OBSOLETE
1, 2, 4 MEG x 32
DRAM SODIMMs
PART NUMBERS
EDO Operating Mode
PART NUMBER
MT2LDT132HG-x X
MT2LDT132HG-x XS
MT4LDT232HG-x X
MT4LDT232HG-x XS
MT8LDT432HG-x X
MT8LDT432HG-x XS
x = speed
CONFIGURATION
1 Meg x 32
1 Meg x 32
2 Meg x 32
2 Meg x 32
4 Meg x 32
4 Meg x 32
REFRESH
Standard
Self
Standard
Self
Standard
Self
EDO PAGE MODE
EDO PAGE MODE, designated by the “X” version, is an
accelerated FAST-PAGE-MODE cycle. The primary advan-
tage of EDO is the availability of data-out even after CAS#
goes back HIGH. EDO provides for CAS# precharge time
(
t
CP) to occur without the output data going invalid. This
elimination of CAS# output control provides for pipelined
READs.
FAST-PAGE-MODE modules have traditionally turned
the output buffers off (High-Z) with the rising edge of
CAS#. EDO operates as any DRAM READ or FAST-PAGE-
MODE READ, except data will be held valid or become
valid after CAS# goes HIGH, as long as RAS# and OE#
are held LOW. (Refer to the 1 Meg x 16 (MT4LC1M16E5)
DRAM data sheet for additional information on EDO
functionality.)
FPM Operating Mode
PART NUMBER
MT2LDT132HG-x
MT2LDT132HG-x S
MT4LDT232HG-x
MT4LDT232HG-x S
MT8LDT432HG-x
MT8LDT432HG-x S
x = speed
CONFIGURATION
1 Meg x 32
1 Meg x 32
2 Meg x 32
2 Meg x 32
4 Meg x 32
4 Meg x 32
REFRESH
Standard
Self
Standard
Self
Standard
Self
REFRESH
Memory cell data is retained in its correct state by main-
taining power and executing any RAS# cycle (READ,
WRITE) or RAS# refresh cycle (RAS#-ONLY, CBR or HID-
DEN) so that all combinations of RAS# addresses are ex-
ecuted at least every
t
REF, regardless of sequence. The CBR
REFRESH cycle will invoke the internal refresh counter for
automatic RAS# addressing.
An optional self refresh mode is also available. The “S”
option allows the user the choice of a fully static, low-power
data retention mode or a dynamic refresh mode at the
extended refresh period of 128ms. The optional self refresh
feature is initiated by performing a CBR REFRESH cycle
and holding RAS# LOW for the specified
t
RASS.
The self refresh mode is terminated by driving RAS#
HIGH for a minimum time of
t
RPS. This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the RAS# LOW-to-HIGH transition. If
the DRAM controller uses a distributed refresh sequence, a
burst refresh is not required upon exiting self refresh.
However, if the DRAM controller utilizes a RAS#-ONLY or
burst refresh sequence, all rows must be refreshed within
the average internal refresh rate, prior to the resumption of
normal operation.
GENERAL DESCRIPTION
The MT2LDT132H(X)(S), MT4LDT232H(X)(S) and
MT8LDT432H(X)(S) are randomly accessed 4MB, 8MB and
16MB memories organized in a small-outline x32 configu-
ration. They are specially processed to operate from 3V to
3.6V for low-voltage memory systems.
During READ or WRITE cycles, each bit is uniquely
addressed through the address bits, which are entered 10/
11 bits (A0 -A9/A10) at a time. RAS# is used to latch the
first 10/11 bits and CAS# the latter 10/11 bits.
READ and WRITE cycles are selected with the WE#
input. A logic HIGH on WE# dictates read mode, while a
logic LOW on WE# dictates write mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE# or
CAS#, whichever occurs last. If WE# goes LOW prior to
CAS# going LOW, the output pin(s) remain open (High-Z)
until the next CAS# cycle.
FAST PAGE MODE
FAST-PAGE-MODE operations allow faster data opera-
tions (READ or WRITE) within a row-address-defined
page boundary. The FAST-PAGE-MODE cycle is always
initiated with a row address strobed in by RAS#, followed
by a column address strobed in by CAS#. Additional col-
umns may be accessed by providing valid column
addresses, strobing CAS# and holding RAS# LOW , thus
executing faster memory cycles. Returning RAS# HIGH
terminates the FAST-PAGE-MODE operation.
STANDBY
Returning RAS# and CAS# HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during
the RAS# HIGH time.
1, 2, 4 Meg x 32 DRAM SODIMMs
DM34.p65 – Rev. 6/98
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998,
Micron Technology, Inc.
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