NOIV1SN1300A,
NOIV2SN1300A
VITA 1300 1.3 Megapixel
150 FPS Global Shutter
CMOS Image Sensor
www.onsemi.com
Features
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SXGA: 1280 x 1024 Active Pixels
4.8
mm
x 4.8
mm
Pixel Size
1/2 inch Optical Format
Monochrome (SN) or Color (SE)
150 Frames per Second (fps) at Full Resolution (LVDS)
37 Frames per Second (fps) at Full Resolution (CMOS)
On-chip 10-bit Analog-to-Digital Converter (ADC)
8-bit or 10-bit Output Mode
Four LVDS Serial Outputs or Parallel CMOS Output
Random Programmable Region of Interest (ROI) Readout
Pipelined and Triggered Global Shutter, Rolling Shutter
On-chip Fixed Pattern Noise (FPN) Correction
Serial Peripheral Interface (SPI)
Automatic Exposure Control (AEC)
Phase Locked Loop (PLL)
High Dynamic Range (HDR)
Dual Power Supply (3.3 V and 1.8 V)
−40°C
to +85°C Operational Temperature Range
48-pin LCC and Bare Die
475 mW Power Dissipation (LVDS)
290 mW Power Dissipation (CMOS)
These Devices are Pb−Free and are RoHS Compliant
Figure 1. VITA 1300 Photograph
Applications
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Machine Vision
Motion Monitoring
Security
Barcode Scanning (2D)
Description
The VITA 1300 is a
1/2
inch Super-eXtended Graphics Array (SXGA) CMOS image sensor with a pixel array of 1280 by 1024.
The high sensitivity 4.8
mm
x 4.8
mm
pixels support pipelined and triggered global shutter readout modes and can also be
operated in a low noise rolling shutter mode. In rolling shutter mode, the sensor supports correlated double sampling readout,
reducing noise and increasing the dynamic range.
The sensor has on-chip programmable gain amplifiers and 10-bit A/D converters. The integration time and gain parameters
can be reconfigured without any visible image artifact. Optionally the on-chip automatic exposure control loop (AEC) controls
these parameters dynamically. The image’s black level is either calibrated automatically or can be adjusted by adding a user
programmable offset.
A high level of programmability using a four wire serial peripheral interface enables the user to read out specific regions
of interest. Up to 8 regions can be programmed, achieving even higher frame rates.
The image data interface of the V1-SN/SE part consists of four LVDS lanes, facilitating frame rates up to 150 frames per
second. Each channel runs at 620 Mbps. A separate synchronization channel containing payload information is provided to
facilitate the image reconstruction at the receive end. The V2-SN/SE part provides a parallel CMOS output interface at reduced
frame rate.
The VITA 1300 is packaged in a 48-pin LCC package and is available in a monochrome and color version.
Contact your local ON Semiconductor office for more information.
©
Semiconductor Components Industries, LLC, 2014
December, 2016
−
Rev. 10
1
Publication Order Number:
NOIV1SN1300A/D
NOIV1SN1300A, NOIV2SN1300A
ORDERING INFORMATION
Part Number
NOIV1SN1300A-QDC
NOIV1SE1300A-QDC
NOIV2SN1300A-QDC
NOIV2SE1300A-QDC
NOIV1SN1300A-XXC
Mono/Color
LVDS Interface mono
LVDS Interface color
CMOS Interface mono
CMOS Interface color
Die sales, mono
Die Sales
Package
48−pin LCC
The V1-SN/SE base part is used to reference the mono and
color versions of the LVDS interface; the V2-SN/SE base
part is used to reference the mono and color versions of the
CMOS interface.
ORDERING CODE DEFINITION
PACKAGE MARK
Following is the mark on the bottom side of the package with Pin 1 to the left center
Line 1:
NOI xxxx 1300A
where xxxx denotes LVDS (V1) / CMOS (V2), mono micro lens (SN) /color micro lens (SE) option
Line 2:
-QDC
Line 3:
AWLYYWW
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2
NOIV1SN1300A, NOIV2SN1300A
CONTENTS
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering Code Definition . . . . . . . . . . . . . . . . . . . . . . 2
Package Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Sensor Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Image Sensor Timing and Readout . . . . . . . . . . . . . .
Additional Features . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Output Format . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifications and Useful References . . . . . . . . . . . . .
Silicon Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
30
33
41
50
66
72
73
74
75
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3
NOIV1SN1300A, NOIV2SN1300A
SPECIFICATIONS
Key Specifications
Table 1. GENERAL SPECIFICATIONS
Parameter
Pixel type
Shutter type
Frame rate
at full resolution
Master clock
Specification
Global shutter pixel architecture
Pipelined and triggered global shutter,
rolling shutter
V1-SN/SE: 150 fps
V2-SN/SE: 37 fps
V1-SN/SE:
62 MHz when PLL is used,
310 MHz (10-bit) / 248 MHz (8-bit)
when PLL is not used
V2-SN/SE: 62 MHz
8 Randomly programmable windows.
Normal, sub-sampled and binned read-
out modes
10-bit, 8-bit
V1-SN/SE: 4 data + sync + clock
V2-SN/SE: 10-bit parallel output,
frame_valid, line_valid, clock
V1-SN/SE:
4 x 620 Mbps (10-bit) /
4 x 496 Mbps (8-bit)
V2-SN/SE: 62 MHz
475 mW for V1-SN/SE in 10-bit mode
290 mW for V2-SN/SE
48-pin LCC, bare die
Table 2. ELECTRO−OPTICAL SPECIFICATIONS
Parameter
Active pixels
Pixel size
Optical format
Conversion gain
Dark noise
Responsivity at 550 nm
Parasitic Light
Sensitivity (PLS)
Full well charge
Quantum efficiency
Pixel FPN
PRNU
MTF
PSNL @ 25°C
Dark signal @ 25°C
Dynamic range
Signal to Noise Ratio
(SNR max)
Specification
1280 (H) x 1024 (V)
4.8
mm
x 4.8
mm
1/2 inch
0.072 LSB10/e
-
90
mV/e
-
2.2 LSB10, 30e
-
in global shutter
0.9 LSB10, 14e
-
in rolling shutter
24 LSB10 /nJ/cm
2
, 4.6 V/lux.s
<1/450
13700 e
-
53% at 550 nm
rolling shutter: 0.5 LSB10
global shutter: 1.0 LSB10
< 2% of signal
60% @ 630 nm - X-dir & Y-dir
100 LSB10/s, 1360 e
-
/s
4.5 e
-
/s, 0.33 LSB10/s
60 dB in rolling shutter mode
53 dB in global shutter mode
41 dB
Windowing
ADC resolution
(1)
LVDS outputs
CMOS outputs
Data rate
Power dissipation
Package type
Table 3. RECOMMENDED OPERATING RATINGS
(Note 2)
Symbol
T
J
Description
Operating temperature range
Min
−40
Max
85
Units
°C
Table 4. ABSOLUTE MAXIMUM RATINGS
(Notes 3 and 4)
Symbol
ABS (1.8 V supply group)
ABS (3.3 V supply group)
T
S
Electrostatic discharge (ESD)
Parameter
ABS rating for 1.8 V supply group
ABS rating for 3.3 V supply group
ABS storage temperature range
ABS storage humidity range at 85°C
Human Body Model (HBM): JS−001−2010
Charged Device Model (CDM): JESD22−C101
LU
Latch-up: JESD−78
2000
500
140
mA
Min
–0.5
–0.5
−40
Max
2.2
4.3
+150
85
Units
V
V
°C
%RH
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The ADC is 11−bit, down−scaled to 10−bit. The VITA 1300 uses a larger word−length internally to provide 10−bit on the output.
2. Operating ratings are conditions in which operation of the device is intended to be functional.
3. ON Semiconductor recommends that customers become familiar with, and follow the procedures in JEDEC Standard JESD625−A. Refer
to Application Note AN52561. Long term exposure toward the maximum storage temperature will accelerate color filter degradation.
4. Caution needs to be taken to avoid
dried stains on the underside of the glass due to condensation. The glass lid glue is permeable and can
absorb moisture if the sensor is placed in a high % RH environment.
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NOIV1SN1300A, NOIV2SN1300A
Table 5. ELECTRICAL SPECIFICATIONS
Boldface limits apply for T
J
= T
MIN
to T
MAX
, all other limits T
J
= +30°C. (Notes 5, 6 and 7)
Parameter
Description
Min
Typ
Max
Units
Power Supply Parameters - V1-SN/SE LVDS
vdd_33
Idd_33
vdd_18
Idd_18
vdd_pix
Idd_pix
Ptot
Pstby_lp
Popt
Supply voltage, 3.3 V
Current consumption 3.3 V supply
Supply voltage, 1.8 V
Current consumption 1.8 V supply
Supply voltage, pixel
Current consumption pixel supply
Total power consumption at vdd_33 = 3.3 V, vdd_18 = 1.8 V
Power consumption in low power standby mode. See Silicon Errata
on page 66
Power consumption at lower pixel rates
Configurable
3.0
90
1.6
45
3.0
0.8
375
3.3
110
1.8
60
3.3
1.8
475
3.6
130
2.0
75
3.6
2.5
575
50
V
mA
V
mA
V
mA
mW
mW
Power Supply Parameters - V2-SN/SE CMOS
vdd_33
Idd_33
vdd_18
Idd_18
vdd_pix
Idd_pix
Ptot
Pstby_lp
Popt
Supply voltage, 3.3 V
Current consumption 3.3 V supply
Supply voltage, 1.8 V
Current consumption 1.8 V supply
Supply voltage, pixel
Current consumption pixel supply
Total power consumption
Power consumption in low power standby mode. See Silicon Errata
on page 66
Power consumption at lower pixel rates
Configurable
220
3.0
70
1.6
4
3.0
3.3
90
1.8
7
3.3
0.5
290
3.6
110
2.0
10
3.6
1
360
50
V
mA
V
mA
V
mA
mW
mW
I/O - V2-SN/SE CMOS (JEDEC- JESD8C-01): Conforming to standard/additional specifications and deviations listed
fpardata
Cout
tr
tf
Data rate on parallel channels (10-bit)
Output load (only capacitive load)
Rise time (10% to 90% of input signal)
Fall time (10% to 90% of input signal)
2.5
2
4.5
3.5
62
10
6.5
5
Mbps
pF
ns
ns
I/O - V1-SN/SE LVDS (EIA/TIA-644): Conforming to standard/additional specifications and deviations listed
fserdata
fserclock
Vicm
Tccsk
Data rate on data channels
DDR signaling - 4 data channels, 1 synchronization channel;
Clock rate of output clock
Clock output for mesochronous signaling
LVDS input common mode level
Channel to channel skew (Training pattern allows per channel skew
correction)
0.3
1.25
620
310
2.2
50
Mbps
MHz
V
ps
V1-SN/SE LVDS Electrical/Interface
fin
fin
tidc
tj
fspi
Input clock rate when PLL used
Input clock when LVDS input used
Input clock duty cycle when PLL used
Input clock jitter
SPI clock rate when PLL used at fin = 62 MHz
40
50
20
10
62
310
60
MHz
MHz
%
ps
MHz
V2-SN/SE CMOS Electrical/Interface
fin
Input clock rate
62
MHz
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