Flexible Input Deterministic Output (fido
®
)
32-Bit Real-Time Communications Controller
Data Sheet
April 10, 2013
fido1100
®
Data Sheet
32-Bit Real-Time Communications Controller
IA211080807-10
UNCONTROLLED WHEN PRINTED OR COPIED
Page 1 of 74
http://www.innovasic.com
Customer Support:
1-888-824-4184
Flexible Input Deterministic Output (fido
®
)
32-Bit Real-Time Communications Controller
Data Sheet
April 10, 2013
Copyright
2013 by Innovasic, Inc.
Published by Innovasic, Inc.
5635 Jefferson St. NE, Suite A, Albuquerque, New Mexico 87109 USA
fido
®
, fido1100
®
, and SPIDER are trademarks of Innovasic, Inc.
I
2
C™ Bus is a trademark of Philips Electronics N.V.
Motorola is a registered trademark of Motorola, Inc.
IA211080807-10
UNCONTROLLED WHEN PRINTED OR COPIED
Page 2 of 74
http://www.innovasic.com
Customer Support:
1-888-824-4184
Flexible Input Deterministic Output (fido
®
)
32-Bit Real-Time Communications Controller
Data Sheet
April 10, 2013
TABLE OF CONTENTS
List of Figures ..................................................................................................................................5
List of Tables ...................................................................................................................................6
1.
Overview.................................................................................................................................7
2.
Features ...................................................................................................................................9
2.1 Core CPU ....................................................................................................................10
2.2 JTAG ...........................................................................................................................10
2.3 Internal Memory and Memory Management ..............................................................11
2.4 External Bus Interface .................................................................................................12
2.5 PMU/UIC/CPU DMA .................................................................................................12
2.6 Internal Peripherals .....................................................................................................13
2.6.1 Timer Counter Units (TCU) ...........................................................................13
2.6.2 Analog-to-Digital Converter (ADC)...............................................................14
2.6.3 Timers .............................................................................................................14
2.7 Power Control .............................................................................................................14
3.
Libraries and Support Tools .................................................................................................15
4.
Packaging, Pin Descriptions, and Physical Dimensions .......................................................16
4.1 PQFP Package .............................................................................................................17
4.1.1 PQFP Pinout ...................................................................................................17
4.1.2 PQFP Physical Dimensions ............................................................................24
4.2 BGA 15- by 15-mm Package ......................................................................................25
4.2.1 BGA 15- by 15-mm Pinout.............................................................................25
4.2.2 BGA 15- by 15-mm Physical Package Dimensions .......................................33
4.2.3 BGA 15- by 15-mm Signal Routing ...............................................................34
4.3 Power and Ground Signals ..........................................................................................36
5.
Electrical Characteristics ......................................................................................................38
6.
Thermal Characteristics ........................................................................................................41
7.
Reset .....................................................................................................................................42
7.1 Overview .....................................................................................................................42
7.2 Signal Considerations and Reset Timing ....................................................................42
7.3 Clock Signals...............................................................................................................44
7.4 Typical Clock Source Implementations ......................................................................44
7.4.1 Normal or Driven Clock Source .....................................................................44
7.4.2 Using an External Crystal ...............................................................................44
7.5 Off-Chip Component Value ........................................................................................46
8.
Signals...................................................................................................................................47
8.1 External Bus Operation ...............................................................................................47
8.1.1 Overview.........................................................................................................47
IA211080807-10
UNCONTROLLED WHEN PRINTED OR COPIED
Page 3 of 74
http://www.innovasic.com
Customer Support:
1-888-824-4184
Flexible Input Deterministic Output (fido
®
)
32-Bit Real-Time Communications Controller
Data Sheet
April 10, 2013
9.
10.
11.
12.
13.
14.
8.2 General Setup and Hold Timing..................................................................................47
8.3 External Bus Timing ...................................................................................................48
Setup and Hold Timing .........................................................................................................49
9.1.1 External Bus Timing for a 32-Bit Transfer (without RDY_N) ......................51
9.1.2 External Bus Timing for a 32-Bit Transfer (with RDY_N) ...........................52
9.1.3 External Bus Timing for 8-Bit/16-Bit Transfer (without RDY_N) ................54
9.1.4 External Bus Timing for 8-Bit/16-Bit Transfer (with RDY_N) .....................55
9.2 SDRAM Timing ..........................................................................................................56
9.2.1 SDRAM CAS Timing.....................................................................................56
9.2.2 SDRAM Row Activation Timing ...................................................................57
9.2.3 SDRAM Read Operation Timing ...................................................................59
9.2.4 SDRAM Read Burst Timing ..........................................................................59
9.2.5 SDRAM Write Operation, Write Burst, Write-to-Write, and Write-to-
Precharge Timing............................................................................................60
JTAG.....................................................................................................................................64
10.1 JTAG Scan Chain Debug Functionality ......................................................................65
Ordering Information ............................................................................................................67
Errata.....................................................................................................................................68
12.1 Summary .....................................................................................................................68
12.2 Detail ...........................................................................................................................68
Revision History ...................................................................................................................72
For Additional Information...................................................................................................74
IA211080807-10
UNCONTROLLED WHEN PRINTED OR COPIED
Page 4 of 74
http://www.innovasic.com
Customer Support:
1-888-824-4184
Flexible Input Deterministic Output (fido
®
)
32-Bit Real-Time Communications Controller
Data Sheet
April 10, 2013
LIST OF FIGURES
Figure 1. Block Diagram for the fido1100......................................................................................8
Figure 2. PQFP Package Diagram ................................................................................................17
Figure 3. PQFP Physical Package Dimensions.............................................................................24
Figure 4. BGA 15- by 15-mm Package Diagram .........................................................................26
Figure 5. BGA 15- by 15-mm Physical Package Dimensions ......................................................33
Figure 6. BGA 15- by 15-mm Signal Routing..............................................................................35
Figure 7. Reset Timing .................................................................................................................43
Figure 8. Extended Reset Timing .................................................................................................43
Figure 9. Driven Clock Source .....................................................................................................45
Figure 10. Crystal Oscillator Third Overtone Off-Chip Components .........................................45
Figure 11. Crystal Oscillator Fundamental Overtone Off-Chip Components ..............................45
Figure 12. Propagation Delay .......................................................................................................49
Figure 13. Setup Time...................................................................................................................49
Figure 14. Hold Time ....................................................................................................................50
Figure 15. Recovery Time ............................................................................................................50
Figure 16. Removal Time .............................................................................................................50
Figure 17. Minimum Pulse Width ................................................................................................51
Figure 18. External Bus Timing for a Single, 32-Bit Cycle (without RDY_N) ...........................52
Figure 19. External Bus Timing for a 32-Bit Transfer (with RDY_N) ........................................53
Figure 20. External Bus Timing for 8-Bit/16-Bit Transfer (without RDY_N).............................54
Figure 21. External Bus Timing for 8-Bit/16-Bit Transfer (with RDY_N) ..................................55
Figure 22. SDRAM CAS Timing .................................................................................................57
Figure 23. Specific Row Activation Timing .................................................................................58
Figure 24. Meeting tRCD (min) When 2 < tRCD (min)/tCK ≤ 3 ................................................58
Figure 25. SDRAM Read Operation Timing ................................................................................59
Figure 26. SDRAM Read Burst Timing .......................................................................................60
Figure 27. SDRAM Write Operation Timing ...............................................................................61
Figure 28. SDRAM Write Burst Timing ......................................................................................62
Figure 29. SDRAM Write-to-Write Timing .................................................................................62
Figure 30. SDRAM Write-to-Precharge Timing ..........................................................................63
Figure 31. JTAG State Machine ...................................................................................................64
Figure 32. JTAG Port Register Interface ......................................................................................65
Figure 33. Timing of JTAG Signals .............................................................................................65
IA211080807-10
UNCONTROLLED WHEN PRINTED OR COPIED
Page 5 of 74
http://www.innovasic.com
Customer Support:
1-888-824-4184
stm32/stm8
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
