2 MEG
X
8, 1 MEG
X
18, 512K
X
36
1.8V V
DD
, HSTL, QDRIIb2 SRAM
18Mb QDR II SRAM
2-WORD BURST
Features
• DLL circuitry for accurate output data placement
• Separate independent read and write data ports with
concurrent transactions
• 100 percent bus utilization DDR READ and WRITE
operation
• Fast clock to valid data times
• Full data coherency, providing most current data
• Two-tick burst counter for low DDR transaction size
• Double data rate operation on read and write ports
• Two input clocks (K and K#) for precise DDR timing at
clock rising edges only
• Two output clocks (C and C#) for precise flight time
and clock skew matching—clock and data delivered
together to receiving device
• Optional-use echo clocks (CQ and CQ#) for flexible
receive data synchronization
• Single address bus
• Simple control logic for easy depth expansion
• Internally self-timed, registered writes
• Core V
DD
= 1.8V (±0.1V); I/O V
DD
Q = 1.5V to V
DD
(±0.1V) HSTL
• Clock-stop capability with µs restart
• 13mm x 15mm, 1mm pitch, 11 x 15 grid FBGA package
• User-programmable impedance output
•
JTAG boundary scan
™
MT54W2MH8B
MT54W1MH18B
MT54W512H36B
Figure 1: 165-Ball FBGA
Table 1:
Valid Part Numbers
DESCRIPTION
2 Meg x 8, QDRIIb2 FBGA
1 Meg x 18, QDRIIb2 FBGA
512K x 36, QDRIIb2 FBGA
PART NUMBER
MT54W2MH8BF-xx
MT54W1MH18BF-xx
MT54W512H36BF-xx
Options
• Clock Cycle Timing
4ns (250 MHz)
5ns (200 MHz)
6ns (167 MHz)
7.5ns (133 MHz)
• Configurations
2 Meg x 8
1 Meg x 18
512K x 36
• Package
165-ball, 13mm x 15mm FBGA
• Operating Temperature Range
Commercial (0°C
£
T
A
£
+70°C)
NOTE
:
Marking
1
-4
-5
-6
-7.5
MT54W2MH8B
MT54W1MH18B
MT54W512H36B
F
None
1. A Part Marking Guide for the FBGA devices can be found on
Micron’s Web site—http://www.micron.com/numberguide.
The Micron
®
QDR™II (Quad Data Rate™) synchro-
nous, pipelined burst SRAM employs high-speed, low-
power CMOS designs using an advanced 6T CMOS
process.
The QDR architecture consists of two separate DDR
(double data rate) ports to access the memory array.
The read port has dedicated data outputs to support
READ operations. The write port has dedicated data
inputs to support WRITE operations. This architecture
eliminates the need for high-speed bus turnaround.
Access to each port is accomplished using a common
address bus. Addresses for reads and writes are latched
on rising edges of the K and K# input clocks, respec-
tively. Each address location is associated with two
words that burst sequentially into or out of the device.
Since data can be transferred into and out of the device
on every rising edge of both clocks (K and K# and C
and C#), memory bandwidth is maximized and system
design is simplified by eliminating bus turnarounds.
General Description
18Mb: 1.8V V
DD
, HSTL, QDRIIb2 SRAM
MT54W1MH18B_H.fm – Rev. H, Pub. 3/03
1
©2003 Micron Technology, Inc.
2 MEG
X
8, 1 MEG
X
18, 512K
X
36
1.8V V
DD
, HSTL, QDRIIb2 SRAM
Depth expansion is accomplished with port selects
for each port (read R#, write W#) which are received at
K rising edge. Port selects permit independent port
operation.
All synchronous inputs pass through registers con-
trolled by the K or K# input clock rising edges. Active
LOW byte writes (BWx#) permit byte or nibble write
selection. Write data and byte writes are registered on
the rising edges of both K and K#. The addressing
within each burst of two is fixed and sequential, begin-
ning with the lowest and ending with the highest
address. All synchronous data outputs pass through
output registers controlled by the rising edges of the
output clocks (C and C# if provided, otherwise K and
K#).
Four balls are used to implement JTAG test capabili-
ties: test mode select (TMS), test data-in (TDI), test
clock (TCK), and test data-out (TDO). JTAG circuitry is
used to serially shift data to and from the SRAM. JTAG
inputs use JEDEC-standard 1.8V I/O levels to shift data
during this testing mode of operation.
The SRAM operates from a 1.8V power supply, and
all inputs and outputs are HSTL-compatible. The
device is ideally suited for applications that benefit
from a high-speed, fully-utilized DDR data bus.
Please refer to Micron’s Web site (www.micron.com/
sramds)
for the latest data sheet.
READ cycles are pipelined. The request is initiated
by asserting R# LOW at K rising edge. Data is delivered
after the next rising edge of the next K# (t + 1), using C
and C# as the output timing references; or K and K#, if
C and C# are tied HIGH. If C and C# are tied HIGH,
they may not be toggled during device operation. Out-
put tri-stating is automatically controlled such that the
bus is released if no data is being delivered. This per-
mits banked SRAM systems with no complex output
enable (OE) timing generation. Back-to-back READ
cycles are initiated every K rising edge.
WRITE cycles are initiated by W# LOW at K rising
edge. The addresses for the WRITE cycle is provided at
the following K# rising edge. Data is expected at the
rising edge of K and K#, beginning at the same K that
initiated the cycle. Write registers are incorporated to
facilitate pipelined, self-timed WRITE cycles and pro-
vide fully coherent data for all combinations of reads
and writes. A read can immediately follow a write, even
if they are to the same address. Although the write data
has not been written to the memory array, the SRAM
will deliver the data from the write register instead of
using the older data from the memory array. The latest
data is always utilized for all bus transactions. WRITE
cycles can be initiated on every K rising edge.
PARTIAL WRITE Operations
BYTE WRITE operations are supported except for
the x8 devices in which nibble write is supported. The
active LOW byte write controls, BWx# (NW#), are regis-
tered coincident with their corresponding data. This
feature can eliminate the need for some READ-MOD-
IFY-WRITE cycles, collapsing it to a single BYTE/NIB-
BLE WRITE operation in some instances.
READ/WRITE Operations
All bus transactions operate on an uninterruptable
burst of two data, requiring one full clock cycle of bus
utilization. The resulting benefit is that short data
transactions can remain in operation on both buses
provided that the address rate can be maintained by
the system (2x the clock frequency).
18Mb: 1.8V V
DD
, HSTL, QDRIIb2 SRAM
MT54W1MH18B_H.fm – Rev. H, Pub. 3/03
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG
X
8, 1 MEG
X
18, 512K
X
36
1.8V V
DD
, HSTL, QDRIIb2 SRAM
Programmable Impedance Output
Buffer
The QDR SRAM is equipped with programmable
impedance output buffers. This allows a user to match
the driver impedance to the system. To adjust the
impedance, an external precision resistor (RQ) is con-
nected between the ZQ ball and V
SS
. The value of the
resistor must be five times the desired impedance. For
example, a 350
W
resistor is required for an output
impedance of 70
W
. To ensure that output impedance
is one-fifth the value of RQ (within 15 percent), the
range of RQ is 175
W
to 350
W
. Alternately, the ZQ ball
can be connected directly to V
DD
Q, which will place
the device in a minimum impedance mode.
Output impedance updates may be required
because variations may occur in supply voltage and
temperature over time. The device samples the value
of RQ. Impedance updates are transparent to the sys-
tem; they do not affect device operation, and all data
sheet timing and current specifications are met during
an update.
The device will power up with an output impedance
set at 50
W
. To guarantee optimum output driver
impedance after power-up, the SRAM needs 1,024
cycles to update the impedance. The user can operate
the part with fewer than 1,024 clock cycles, but optimal
output impedance is not guaranteed.
automatically resets the DLL when the absence of
input clock is detected. See Micron Technical Note TN-
54-02 for more information on clock DLL start-up pro-
cedures.
Single Clock Mode
The SRAM can be used with the single K, K# clock
pair by tying C and C# HIGH. In this mode the SRAM
will use K and K# in place of C and C#. This mode pro-
vides the most rapid data output but does not com-
pensate for system clock skew and flight times.
The output echo clocks are precise references to
output data. CQ and CQ# are both rising edge and fall-
ing edge accurate and are 180° out of phase. Either or
both may be used for output data capture. K or C rising
edge triggers CQ rising and CQ# falling edge. CQ rising
edge indicates first data response for QDRI and DDRI
(version 1, non-DLL) SRAM, while CQ# rising edge
indicates first data response for QDRII and DDRII (ver-
sion 2, DLL) SRAM.
Depth Expansion
Port select inputs are provided for the read and
write ports. This allows for easy depth expansion. Both
port selects are sampled on the rising edge of K only.
Each port can be independently selected and dese-
lected and does not affect the operation of the oppo-
site port. All pending transactions are completed prior
to a port deselecting. Depth expansion requires repli-
cating R# and W# control signals for each bank if it is
desired to have the bank independent of READ and
WRITE operations.
Clock Considerations
This device utilizes internal delay-locked loops for
maximum output data valid window. It can be placed
into a stopped-clock state to minimize power with a
modest restart time of 1,024 clock cycles. Circuitry
18Mb: 1.8V V
DD
, HSTL, QDRIIb2 SRAM
MT54W1MH18B_H.fm – Rev. H, Pub. 3/03
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG
X
8, 1 MEG
X
18, 512K
X
36
1.8V V
DD
, HSTL, QDRIIb2 SRAM
Figure 2: Functional Block Diagram
2 Meg x 8; 1 Meg x 18; 512K x 36
n
ADDRESS
R#
W#
K
K#
n
ADDRESS
REGISTRY
& LOGIC
W#
NWx# or BWx#
a
DATA
REGISTRY
& LOGIC
2a
WR
R E
I G
T
E 2
WD
R R
I I
T V
E E
R
2 xa
MEMORY
ARRAY
n
D (Data In)
R#
K
K#
K
S
E A
NM
S P
E S
2a
MUX
RO
E U
G T
P
AU
T
C
2a
O
U
T
P
U
T
S
E
L
E
C
T
O
U
T
P
U
T
B
U
F
F
E
R
a
Q
(Data Out)
2
C, C#
or
K, K#
CQ, CQ#
(Echo Clock Out)
NOTE
:
1. Figure 2 illustrates simplified device operation. See truth table, ball descriptions, and timing diagrams for detailed
information.
2. For 2 Meg x 8, n = 20, a = 8; NWx# = 2 separate nibble writes.
For 1 Meg x 18, n = 19, a = 18; BWx# = 2 separate byte writes.
For 512K x 36, n = 18, a = 36; BWx# = 2 separate byte writes.
18Mb: 1.8V V
DD
, HSTL, QDRIIb2 SRAM
MT54W1MH18B_H.fm – Rev. H, Pub. 3/03
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG
X
8, 1 MEG
X
18, 512K
X
36
1.8V V
DD
, HSTL, QDRIIb2 SRAM
Figure 3: Application Example
SRAM #1
Vt
R
D
SA
B
R W W
# # #
ZQ
Q
C C# K K#
R = 250Ω
D
SA
SRAM #4
B
R W W
# # #
ZQ
Q
C C# K K#
R = 250Ω
DATA IN
DATA OUT
Address
Read#
BUS
Write#
MASTER
BW#
R
Vt
Vt
(CPU
or
ASIC)
Source K
Source K#
Delayed K
Delayed K#
R
R = 50Ω Vt = V
REF
/2
NOTE
:
1. In this approach, the second clock pair drives the C and C# clocks but is delayed such that return data meets data
setup and hold times at the bus master.
2. Consult Micron Technical Notes for more thorough discussions of clocking schemes.
3. Data capture is possible using only one of the two signals. CQ and CQ# clocks are optional use outputs.
4. For high frequency applications (200 MHz and faster) the CQ and CQ# clocks (for data capture) are recommended
over the C and C# clocks (for data alignment). The C and C# clocks are optional use inputs.
18Mb: 1.8V V
DD
, HSTL, QDRIIb2 SRAM
MT54W1MH18B_H.fm – Rev. H, Pub. 3/03
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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