8Mb: 512K x 18, 256K x 32/36
3.3V I/O, PIPELINED, DCD SYNCBURST SRAM
8Mb SYNCBURST
SRAM
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
™
MT58L512L18D, MT58L256L32D,
MT58L256L36D
3.3V V
DD
, 3.3V I/O, Pipelined, Double-
Cycle Deselect
Fast clock and OE# access times
Single +3.3V +0.3V/-0.165V power supply (V
DD
)
Separate +3.3V isolated output buffer supply (V
DD
Q)
SNOOZE MODE for reduced-power standby
Common data inputs and data outputs
Individual BYTE WRITE control and GLOBAL WRITE
Three chip enables for simple depth expansion and
address pipelining
Clock-controlled and registered addresses, data I/Os
and control signals
Internally self-timed WRITE cycle
Burst control (interleaved or linear burst)
Automatic power-down for portable applications
100-pin TQFP package
165-pin FBGA package
Low capacitive bus loading
x18, x32, and x36 versions available
100-Pin TQFP**
165-Pin FBGA
OPTIONS
• Timing (Access/Cycle/MHz)
3.5ns/6ns/166 MHz
4.0ns/7.5ns/133 MHz
5ns/10ns/100 MHz
• Configurations
512K x 18
256K x 32
256K x 36
• Packages
100-pin TQFP (2-chip enable)
100-pin TQFP (3-chip enable)
165-pin, 13mm x 15mm FBGA
• Operating Temperature Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)**
Part Number Example
MARKING
-6
-7.5
-10
MT58L512L18D
MT58L256L32D
MT58L256L36D
NOTE:
1. JEDEC-standard MS-026 BHA (LQFP).
T
S
F*
None
IT
GENERAL DESCRIPTION
The Micron
®
SyncBurst
™
SRAM family employs high-
speed, low-power CMOS designs that are fabricated us-
ing an advanced CMOS process.
Micron’s 8Mb SyncBurst SRAMs integrate a 512K x 18,
256K x 32, or 256K x 36 SRAM core with advanced syn-
chronous peripheral circuitry and a 2-bit burst counter.
All synchronous inputs pass through registers controlled
by a positive-edge-triggered single-clock input (CLK).
The synchronous inputs include all addresses, all data
inputs, active LOW chip enable (CE#), two additional
chip enables for easy depth expansion (CE2, CE2#), burst
control inputs (ADSC#, ADSP#, ADV#), byte write
enables (BWx#) and global write (GW#). Note that CE2#
is not available on the T Version.
MT58L512L18DT-7.5
* A Part Marking Guide for the FBGA devices can be found on Micron’s
Web site—http://www.micron.com/support/index.html.
** Industrial temperature range offered in specific speed grades and
configurations. Contact factory for more information.
8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM
MT58L512L18D_D.p65 – Rev. 2/02
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
3.3V I/O, PIPELINED, DCD SYNCBURST SRAM
FUNCTIONAL BLOCK DIAGRAM
512K x 18
19
SA0, SA1, SA
MODE
ADV#
CLK
ADDRESS
REGISTER
19
17
19
2
SA0-SA1
SA1'
BINARY Q1
COUNTER AND
LOGIC
CLR
Q0
SA0'
ADSC#
ADSP#
BYTE “b”
WRITE REGISTER
9
BYTE “b”
WRITE DRIVER
9
512K x 9 x 2
MEMORY
ARRAY
9
18
SENSE 18
AMPS
BWb#
OUTPUT
18
REGISTERS
OUTPUT
BUFFERS
E
18
BWa#
BWE#
GW#
CE#
CE2
CE2#
OE#
BYTE “a”
WRITE REGISTER
9
BYTE “a”
WRITE DRIVER
DQs
DQPa
DQPb
ENABLE
REGISTER
18
PIPELINED
ENABLE
2
INPUT
REGISTERS
FUNCTIONAL BLOCK DIAGRAM
256K x 32/36
18
SA0, SA1, SA
ADDRESS
REGISTER
16
SA0-SA1
18
MODE
ADV#
CLK
Q1
SA1'
BINARY
COUNTER
SA0'
CLR
Q0
ADSC#
ADSP#
BWd#
BYTE “d”
WRITE REGISTER
BYTE “c”
WRITE REGISTER
9
BYTE
“d”
WRITE DRIVER
BYTE
“c”
WRITE DRIVER
BYTE
“b”
WRITE DRIVER
BYTE
“a”
WRITE DRIVER
9
BWc#
9
9
256K x 8 x 4
(x32)
256K x 9 x 4
(x36)
36
SENSE
AMPS
36
OUTPUT
REGISTERS
36
BWb#
BYTE “b”
WRITE REGISTER
9
9
MEMORY
ARRAY
OUTPUT
BUFFERS
E
DQs
DQPa
36
DQPd
BWa#
BWE#
GW#
CE#
CE2
CE2#
OE#
BYTE “a”
WRITE REGISTER
9
9
ENABLE
REGISTER
36
PIPELINED
ENABLE
4
INPUT
REGISTERS
NOTE:
Functional block diagrams illustrate simplified device operation. See truth tables, pin descriptions, and timing diagrams
for detailed information.
8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM
MT58L512L18D_D.p65 – Rev. 2/02
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
3.3V I/O, PIPELINED, DCD SYNCBURST SRAM
GENERAL DESCRIPTION (continued)
Asynchronous inputs include the output enable (OE#),
clock (CLK) and snooze enable (ZZ). There is also a burst
mode input (MODE) that selects between interleaved
and linear burst modes. The data-out (Q), enabled by
OE#, is also asynchronous. WRITE cycles can be from
one to two bytes wide (x18) or from one to four bytes wide
(x32/x36), as controlled by the write control inputs.
Burst operation can be initiated with either address
status processor (ADSP#) or address status controller
(ADSC#) inputs. Subsequent burst addresses can be in-
ternally generated as controlled by the burst advance
input (ADV#).
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes to
be written. During WRITE cycles on the x18 device, BWa#
controls DQa pins and DQPa; BWb# controls DQb pins
and DQPb. During WRITE cycles on the x32 and x36
devices, BWa# controls DQa pins and DQPa; BWb# con-
trols DQb pins and DQPb; BWc# controls DQc pins and
DQPc; BWd# controls DQd pins and DQPd. GW# LOW
causes all bytes to be written. Parity bits are only avail-
able on the x18 and x36 versions.
This device incorporates an additional pipelined en-
able register which delays turning off the output buffer
an additional cycle when a deselect is executed. This
feature allows depth expansion without penalizing sys-
tem performance.
Micron’s 8Mb SyncBurst SRAMs operate from a +3.3V
V
DD
power supply, and all inputs and outputs are TTL-
compatible. The device is ideally suited for Pentium
®
and PowerPC pipelined systems and systems that benefit
from a very wide, high-speed data bus. The device is also
ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-wide
applications.
Please refer to Micron’s Web site (www.micron.com/
sramds)
for the latest data sheet.
TQFP PINOUTS
At the time of the writing of this data sheet, there are
two pinouts in the industry. Micron will support both
pinouts for this part.
8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM
MT58L512L18D_D.p65 – Rev. 2/02
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
3.3V I/O, PIPELINED, DCD SYNCBURST SRAM
TQFP PIN ASSIGNMENT TABLE
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
x32/x36
NF/DQPc*
DQc
DQc
V
DD
Q
V
SS
NC
DQc
NC
DQc
DQb
DQc
DQb
DQc
V
SS
V
DD
Q
DQb
DQc
DQb
DQc
V
DD
V
DD
NC
V
SS
DQb
DQd
DQb
DQd
V
DD
Q
V
SS
DQb
DQd
DQb
DQd
DQPb
DQd
NC
DQd
x18
NC
NC
NC
PIN #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
x18
x32/x36
V
SS
V
DD
Q
DQd
DQd
NF/DQPd*
MODE
SA
SA
SA
SA
SA1
SA0
DNU
DNU
V
SS
V
DD
NF
NF (T Version)
SA
(S Version)
SA
SA
SA
SA
SA
SA
SA
NC
NC
NC
PIN #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
x32/x36
NF/DQPa*
DQa
DQa
V
DD
Q
V
SS
NC
DQa
NC
DQa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
ZZ
V
DD
NC
V
SS
DQa
DQb
DQa
DQb
V
DD
Q
V
SS
DQa
DQb
DQa
DQb
DQPa
DQb
NC
DQb
x18
NC
NC
NC
PIN #
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
x18
x32/x36
V
SS
V
DD
Q
DQb
DQb
NF/DQPb*
SA
SA
ADV#
ADSP#
ADSC#
OE#
BWE#
GW#
CLK
V
SS
V
DD
SA
(T Version)
CE2# (S Version)
BWa#
BWb#
NC
BWc#
NC
BWd#
CE2
CE#
SA
SA
NC
NC
SA
*No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version.
8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM
MT58L512L18D_D.p65 – Rev. 2/02
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
3.3V I/O, PIPELINED, DCD SYNCBURST SRAM
Pin Assignment (Top View)
100-Pin TQFP, 2-Chip Enable,
T Version
SA
NC
NC
V
DD
Q
V
SS
NC
DQPa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
NC
NC
V
SS
V
DD
Q
NC
NC
NC
SA
SA
ADV#
ADSP#
ADSC#
OE#
BWE#
GW#
CLK
V
SS
V
DD
SA
BWa#
BWb#
NC
NC
CE2
CE#
SA
SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
49
82
48
83
47
84
46
85
45
86
44
87
43
88
42
89
41
90
40
91
39
92
38
93
37
94
36
95
35
96
34
97
33
98
32
99
31
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
x18
SA
SA
SA
SA
SA
SA
SA
NF
NF
V
DD
V
SS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
SA
SA
ADV#
ADSP#
ADSC#
OE#
BWE#
GW#
CLK
V
SS
V
DD
SA
BWa#
BWb#
BWc#
BWd#
CE2
CE#
SA
SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
49
82
48
83
47
84
46
85
45
86
44
87
43
88
42
89
41
90
40
91
39
92
38
93
37
94
36
95
35
96
34
97
33
98
32
99
31
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NF/DQPb*
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQb
DQb
V
SS
V
DD
Q
DQb
DQb
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
NF/DQPa*
NC
NC
NC
V
DD
Q
V
SS
NC
NC
DQb
DQb
V
SS
V
DD
Q
DQb
DQb
V
DD
V
DD
NC
V
SS
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQPb
NC
V
SS
V
DD
Q
NC
NC
NC
x32/x36
SA
SA
SA
SA
SA
SA
SA
NF
NF
V
DD
V
SS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
*No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version.
8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM
MT58L512L18D_D.p65 – Rev. 2/02
NF/DQPc*
DQc
DQc
V
DD
Q
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DD
Q
DQc
DQc
V
DD
V
DD
NC
V
SS
DQd
DQd
V
DD
Q
V
SS
DQd
DQd
DQd
DQd
V
SS
V
DD
Q
DQd
DQd
NF/DQPd*
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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