NTMD4N03, NVMD4N03
Power MOSFET
Features
4 A, 30 V, N−Channel SO−8 Dual
•
Designed for use in low voltage, high speed switching applications
•
Ultra Low On−Resistance Provides
Higher Efficiency and Extends Battery Life
−
R
DS(on)
= 0.048
W,
V
GS
= 10 V (Typ)
−
R
DS(on)
= 0.065
W,
V
GS
= 4.5 V (Typ)
Miniature SO−8 Surface Mount Package
−
Saves Board Space
Diode is Characterized for Use in Bridge Circuits
Diode Exhibits High Speed, with Soft Recovery
NVMD Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable*
These Devices are Pb−Free and are RoHS Compliant
DC−DC Converters
Computers
Printers
Cellular and Cordless Phones
Disk Drives and Tape Drives
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•
•
•
•
•
•
•
•
•
•
V
DSS
30 V
R
DS(ON)
Typ
48 mW @ V
GS
= 10 V
I
D
Max
4.0 A
N−Channel
D
D
Applications
G
S
G
S
8
1
SOIC−8
SUFFIX NB
CASE 751
STYLE 11
MARKING DIAGRAM*
AND PIN ASSIGNMENT
D1 D1 D2 D2
8
E4N03
AYWW
G
G
1
S1 G1 S2 G2
E4N03 = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
= Pb−Free Package
G
(Note: Microdot may be in either location)
MAXIMUM RATINGS
(T
J
= 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Gate−to−Source Voltage
−
Continuous
Drain Current
−
Continuous @ T
A
= 25°C
−
Single Pulse (tp
≤
10
ms)
Total Power Dissipation
@ T
A
= 25°C (Note 1)
Operating and Storage
Temperature Range
Single Pulse Drain−to−Source
Avalanche Energy
−
Starting T
J
= 25°C
(V
DD
= 25 Vdc, V
GS
= 5.0 Vdc,
Peak I
L
= 4.45 Apk, L = 8 mH,
R
G
= 25
W)
Thermal Resistance
−
Junction−to−Ambient (Note 1)
Maximum Lead Temperature for
Soldering Purposes for 10 seconds
Symbol
V
DSS
V
GS
I
D
I
DM
P
D
T
J
, T
stg
E
AS
Value
30
"20
4.0
12
2.0
−55
to
+150
80
Unit
V
V
Adc
Apk
W
°C
mJ
*For additional marking information, refer to
Application Note AND8002/D.
R
qJA
T
L
62.5
260
°C/W
°C
ORDERING INFORMATION
Device
NTMD4N03R2G
NVMD4N03R2G*
Package
SOIC−8
(Pb−Free)
SOIC−8
(Pb−Free)
Shipping
†
2500 / Tape &
Reel
2500 / Tape &
Reel
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using 1″ pad size, t
≤
10 s
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D
©
Semiconductor Components Industries, LLC, 2013
August, 2013
−
Rev. 4
1
Publication Order Number:
NTMD4N03R2/D
NTMD4N03, NVMD4N03
ELECTRICAL CHARACTERISTICS
(T
C
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 250
mA)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(V
DS
= 30 Vdc, V
GS
= 0 Vdc, T
J
= 25°C)
(V
DS
= 30 Vdc, V
GS
= 0 Vdc, T
J
= 125°C)
Gate−Body Leakage Current
(V
GS
=
±20
Vdc, V
DS
= 0 Vdc)
ON CHARACTERISTICS
(Note 2)
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= 250
mAdc)
Temperature Coefficient (Negative)
Static Drain−to−Source On−State Resistance
(V
GS
= 10 Vdc, I
D
= 4 Adc)
(V
GS
= 4.5 Vdc, I
D
= 2 Adc)
Forward Transconductance
(V
DS
= 3 Vdc, I
D
= 2 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS
(Notes 2 & 3)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(V
DS
= 10 Vdc,
V
GS
= 10 Vdc,
I
D
= 3.5 A)
(V
DD
= 20 Vdc, I
D
= 2 A,
V
GS
= 10 V,
R
G
= 2
W)
t
d(on)
t
r
t
d(off)
t
f
Q
T
Q
1
Q
2
V
SD
t
rr
t
a
t
b
Q
RR
−
−
−
−
−
−
−
−
−
−
−
−
−
7.0
14
16
10
8.0
1.1
1.9
0.82
0.63
14
10
4.0
0.008
15
30
30
20
16
−
−
1.0
−
−
−
−
−
mC
Vdc
ns
nC
ns
(V
DS
= 20 Vdc, V
GS
= 0 Vdc,
f = 1.0 MHz)
C
iss
C
oss
C
rss
−
−
−
285
95
35
400
135
70
pF
V
GS(th)
1.0
−
−
−
−
1.9
4.2
0.048
0.065
6.0
3.0
−
0.060
0.080
−
Vdc
mV/°C
W
V
(BR)DSS
30
−
−
−
−
−
32
−
−
−
−
−
1.0
10
100
Vdc
mV/°C
mAdc
Symbol
Min
Typ
Max
Unit
I
DSS
I
GSS
nAdc
R
DS(on)
g
FS
Mhos
BODY−DRAIN DIODE RATINGS
(Note 2)
Diode Forward On−Voltage
Reverse Recovery Time
(I
S
= 2 A, V
GS
= 0 V,
dI
S
/dt = 100 A/ms)
Reverse Recovery Stored Charge
(I
S
= 2 A, dI
S
/dt = 100 A/ms, V
GS
= 0 V)
2. Pulse Test: Pulse Width
≤
300
ms,
Duty Cycle
≤
2%.
3. Switching characteristics are independent of operating junction temperature.
(I
S
= 2 Adc, V
GS
= 0 V)
(I
S
= 2 Adc, V
GS
= 0 V, T
J
= 150°C)
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2
NTMD4N03, NVMD4N03
TYPICAL MOSFET ELECTRICAL CHARACTERISTICS
8
I
D
, DRAIN CURRENT (AMPS)
8V
6
6V
5V
4
V
GS
= 3 V
4.5 V
7
I
D
, DRAIN CURRENT (AMPS)
6
5
4
3
2
1
0
0
1
T
J
= 25°C
T
J
= 125°C
2
V
DS
≥
10 V
10 V
4V
3.6 V
2
0
T
J
= 25°C
0
0.2
0.4
0.6
0.8
1.0
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
T
J
=
−55°C
3
4
5
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
R
DS(on)
, DRAIN−TO−SOURCE RESISTANCE (W)
0.10
R
DS(on)
, DRAIN−TO−SOURCE RESISTANCE (W)
0.10
Figure 2. Transfer Characteristics
V
GS
= 10
T = 125°C
T
J
= 25°C
0.08
V
GS
= 4.5 V
0.06
0.04
0.02
0
V
GS
= 10 V
0.075
0.05
T = 25°C
T =
−55°C
0.025
0
2
3
4
5
6
7
8
2
3
4
5
6
7
8
I
D
, DRAIN CURRENT (AMPS)
R
DS(on)
, DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
I
D
, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current
and Temperature
1.5
1.375
1.25
1.125
1
0.875
0.75
−50
10
I
D
= 2 A
V
GS
= 10 V
I
DSS
, LEAKAGE (nA)
1000
10,000
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
V
GS
= 0 V
T
J
= 150°C
100
T
J
= 125°C
−25
0
25
50
75
100
125
150
0
5
10
15
20
25
30
T
J
, JUNCTION TEMPERATURE (°C)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
NTMD4N03, NVMD4N03
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
−
V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
−
V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
800
C
iss
C, CAPACITANCE (pF)
600
C
rss
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
T
J
= 25°C
400
C
iss
200
C
oss
V
DS
= 0 V
V
GS
= 0 V
C
rss
25
0
10
5
0
5
10
15
20
V
GS
V
DS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE
VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
NTMD4N03, NVMD4N03
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
10
8
6
4
2
0
30
V
GS
20
V
DS
Q
1
Q
2
10
I
D
= 4 A
T
J
= 25°C
0
1
2
3
4
5
6
7
8
9
10
0
100
t
d(off)
t
f
t
r
t, TIME (ns)
10
t
d(on)
Q
T
V
DD
= 15 V
I
D
= 4 A
V
GS
= 10 V
1
1
10
R
G
, GATE RESISTANCE (W)
100
Q
g
, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, t
rr
, due
to the storage of minority carrier charge, Q
RR
, as shown in
the typical reverse recovery wave form of Figure 14. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
like a diode with short t
rr
and low Q
RR
specifications to
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
4
I
S
, SOURCE CURRENT (AMPS)
V
GS
= 0 V
T
J
= 25°C
3
high di/dts. The diode’s negative di/dt during t
a
is directly
controlled by the device clearing the stored charge.
However, the positive di/dt during t
b
is an uncontrollable
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of t
b
/t
a
serves as a good indicator of recovery
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter t
rr
), have less stored charge and a softer
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.
2
1
0
0.5
0.6
0.7
0.8
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
0.9
Figure 10. Diode Forward Voltage versus Current
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5
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