NCP81038
Synchronous Buck Controller
with Auto Power Saving
Mode and Built-In LDO
NCP81038 is a dual synchronous buck controller that is optimized
for converting the battery voltage or adaptor voltage into multiple
power rails required in desktop and notebook system. NCP81038
consists of two buck switching controllers with fixed 5.0 V output on
channel 2, 3.3 V on channel 1 and two on−board LDOs with three
outputs: 5 V / 60 mA and 3.3 V or 12 V / 10 mA. NCP81038 supports
high efficiency, fast transient response and provides power good
signals. ON Semiconductor proprietary adaptive−ripple control
enables seamless transition from CCM to DCM, where converter runs
at reduced switching frequency with much higher efficiency at light
load. The part operates with supply voltage ranging from 5.5 V to
28 V. NCP81038 is available in a 28−pin QFN package.
Features
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MARKING
DIAGRAM
1
28 PIN QFN, 4x4
MN SUFFIX
CASE 485AR
81038
A
L
Y
W
G
81038
ALYWG
G
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Applications
•
Desktop / Notebook Computers
•
System Power Supplies
•
I/O Power Supplies
ORDERING INFORMATION
Device
NCP81038MNTWG
Package
QFN−28
(Pb−Free)
Shipping
†
4,000 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2013
October, 2013
−
Rev. 10
1
FB2
COMP2
EN2/SS2
PG
EN1/SS1
COMP1
FB1
(Top View)
Publication Order Number:
NCP81038/D
Wide Input Voltage Range: from 5.5 V to 28 V
Built−in 5 V / 60 mA LDO
Built−in selectable 3.3 V or 12 V / 10 mA LDO
Three Selectable Fixed Frequency 300 KHz, 400 KHz or 600 KHz
180 Interleaved Operation Between the Two Channels in
Continue−Conduction−Mode (CCM)
Selected Power−Saving Mode/Forced PWM Mode
Transient−Response−Enhancement (TRE) Control
Input Supply Voltage Feed Forward Control
Resistive or Lossless Inductor’s DCR Current Sensing
Over−Temperature Protection
Internal Fixed 8.5 ms Soft−Start
Fixed Output Voltages 5 V and 3.3 V
Power Good Outputs for Both Channels
Built−in Adaptive Gate Drivers
Output Discharge Operation
Built−in Over−Voltage, Under−Voltage Protection
Accurate Over−Current Protection
Thermal Shutdown
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
5V_LDOBYP
5V_LDOOUT
5V_LDOEN
SKIP
LDO2_EN
LDO2_OUT
VIN
GH2
BST2
SWN2
GL2
PGND2
CSP2
CSN2
28
1
GND
GH1
BST1
SWN1
GL1/FSET
PGND1
CSP1
CSN1
NCP81038
VIN
5V_LDOOUT
−
+
5V_LDOEN
ENABLE
+
−
5V_LDOBYP
LDO
VREF
LDO2_OUT
−
+
LDO2_EN
ENABLE
CSP1
CSN1
+
−
CSA
Control Logic
Ramp Generator
And
PWM Logic
SKIP
BST1
GH1
SW1
5V_LDOOUT
UVLO,
UVP, OVP,
Power Good
OCP, TSD and
Protection
COMP1
Vbias
VREF
+ E/A
SS
−
FB1
OC & TRE Detection
EN1
PG
GND
PG1
Vbias
VIN
GL1/
FSET
PGND1
PG2
Switcher 1 Shown
Figure 1. Block Diagram
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NCP81038
Table 1. PIN DESCRIPTIONS
Pin
No.
1, 21
2, 20
3, 19
4
18
5, 17
6, 16
7, 15
8, 14
9, 13
10, 12
11
22
23
24
Symbol
GH1, GH2
BST1, BST2
SWN1, SWN2
GL2
GL1/FSET
PGND1, PGND2
CSP1, CSP2
CSN1, CSN2
FB1, FB2
COMP1, COMP2
EN1, EN2
PG
VIN
LDO2_OUT
LDO2_EN
Description
Gate driver output of the top N−channel MOSFET.
Top gate driver input supply, a bootstrap capacitor connection between SWNx and this pin.
Switch node between the top MOSFET and bottom MOSFET.
Gate driver output of bottom N−channel MOSFET in channel2.
Gate driver output of bottom N−channel MOSFET in channel1. And it is also used to set up switching
frequency by connecting a resistor from this pin to ground.
Power ground for channel 1 & 2.
Inductor current differential sense non−inverting input.
Inductor current differential sense inverting input.
Output voltage feed back.
Output of the error amplifier.
Channel 1 and channel 2 enable pin. Short this pin to ground to disable the switcher channel. Pull this
pin high to enable the switcher channel.
Power good indicator for both output voltages. Open−drain output.
Battery or Adaptor input voltage
Second internal LDO output. A capacitor of minimum 1.0
mF
is recommended to connect between this
pin and ground.
Enable for second internal LDO
−
Tie to VCC to setup LDO2 output at 12 V
−
Tie to 1/2VCC to setup LDO2 output at 3.3 V
−
Tie to ground to disable LDO
DCM programming pin:
−
Ground this pin to setup automatic CCM−DCM transfer with 33 KHz minimum switching
frequency limitation;
−
Connect this pin to VCC to force CCM operation;
−
Leave this pin open to give automatic CCM−DCM transfer with 33 KHz minimum switching
frequency for channel 1 but forced CCM for channel 2.
Enable for internal 5 V LDO.
The output for internal 5 V LDO. A capacitor of minimum 4.7
mF
is recommended to connect between
this pin and ground.
5 V LDO bypass pin.
GND.
25
SKIP
26
27
28
5V_LDOEN
5V_LDOOUT
5V_LDOBYP
E−Pad
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NCP81038
5V_LDO
10 K
EN5
SKIP
LDO2_OUT
(3.3 V)
VIN
10 K
VOUT1
5V_LDOOUT
5V_LDOBYP
LDO2_OUT
5V_LDOEN
LDO2_EN
22
mFx2
VIN
21
20
19
GH1
BST1
SWN1
GL1/FSET
PGND1
0.1
mF
3.3
mH
Vout1
3.3 V / 6.0 A
18
17
16 CSP1
CSN1
15
FB1
Vout2
5.0 V / 6.0 V
GH2
BST2 1
0.1
mF
2
SWN2
3
GL2
4
PGND2
5
CSP2
6
CSN2
7
28
27
26 25 24 23 22
AGND
8
FB2
9
COMP2
10 11 12 13 14
EN2/SS2
EN1/SS1
COMP1
4
Figure 2. Application Circuit
Table 2. ABSOLUTE MAXIMUM RATINGS
(Note 1)
VIN to GND, 5V_LDOEN to GND
SWN1, SWN2 to GND
BST1, BST2 to GND
GH1, GH2 to GND
PGND1, PGND2
All other pin
Operating Temperature Range, T
A
Junction Temperature, T
J
Storage Temperature Range, T
S
Pkg Power Dissipation (TA = +25°C), P
D
(Note 2)
−0.3
V (DC) to 28 V
−1.0
V for T < 100 n
−0.6
V to 28 V,
−10.0
V for T < 20 ns
−0.6
V to 34 V
−0.6
V to 34 V,
−5.0
V for T < 100 ns
−0.3
V to 0.3 V
−0.3
V to 6.0 V,
−1.0
V for T < 100 ns
0°C to +85°C
−40°C
to +150°C
−55°C
to +150°C
2.45 W max
R
qJA
= 51°C/W
R
qJ−Lead
= 26°C/W
R
qJ−BoardTop
= 3.2°C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Operation at
−40°C
to 0°C guaranteed by design, not production tested.
2. These data are based on JEDEC JESD51.7 highly conductive PCB multiple layer PCB (2 power and/or 2 ground planes 76 mm x 76 mm
1 oz each) connected by 20 thermal vias. 100 sq mm Cu heat spreader, 2 oz.
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PG
SKIP
NCP81038
Table 3. ELECTRICAL CHARACTERISTICS
Parameter
POWER SUPPLY
Input Supply Voltage
INTERNAL LDO OUTPUT
5V_LDOOUT Voltage
5V_LDOOUT Current
5V_LDO Switch to Bypass Threshold
5V_LDOOUT to 5V_IDOBYP Impedance
Hysteresis
LDO2_OUT Voltage
LDO2_EN = VCC, VIN = 15 V,
Load Current = 10 mA
LDO2_EN = 1/2 VCC, VIN = 15 V,
Load Current = 10 mA
LDO2_OUT Current
SUPPLY CURRENT
BSTx Quiescent Current
BSTx Shutdown Supply Current
Vin Pin Supply Current
Shutdown Current
I
VIN_SD
I
BST
I
BST_SD
V
FB
= 1.5 V, EN = 5.0
(No Switching), GH and GL are open
EN = 0, BST = 5 V, SWN = 0
Iload = 0
EN1, EN2, LDOEN, LDO2_EN = 0
EN1, EN2, LDOEN = 5 V,
LDO2_EN = 5 V
EN1, EN2 = 0, LDOEN = 5 V,
LDO2_EN = 2.5 V
EN1, EN2 = 0, LDOEN = 5 V,
LDO2_EN =
0
OSCILLATOR
Oscillator Frequency
Fsw
Rset = 1.8 k
Rset = 9.1 k
Rset = 16 k
Oscillator Frequency Accuracy
ERROR AMPLIFIER
Open Loop DC Gain (Note 3)
Open Loop Unity Gain Bandwidth (Note 3)
Open Loop Phase Margin (Note 3)
Input Bias Current (Note 3)
Input Offset Voltage (Note 3)
Slew Rate
Maximum Output Voltage
Minimum Output Voltage
Output Source Current
Output Sink Current
3. Guaranteed by Design
4. Parameters are for design only, not for product test.
V+ = V− = 0.8 V
COMP pin to GND = 10 pF
10 mV of overdrive, I
SOURCE
= 2.0 mA
10 mV of overdrive, I
SINK
= 2.0 mA
10 mV of overdrive, V
out
= 3.5 V
10 mV of overdrive, V
out
= 1.0 V
2.0
2.0
3.3
0.3
F
0dB,EA
80
10
60
−200
−1.0
2.5
200
1.0
15
dB
MHz
deg
nA
mV
V/ms
V
V
mA
mA
270
340
540
300
400
600
330
460
660
±10
KHz
KHz
KHz
%
2.0
5.0
1.15
1.57
1.11
0.3
6.0
mA
mA
mA
mA
mA
mA
mA
LDOBYP = 5 V
100
11.4
3.2
10
VIN =12 V, I
5V_LDOOUT
= 60 mA
VIN =12 V, EN1 = EN2 = 0
4.7
1.0
200
12
3.3
15
12.6
3.46
4.85
5.0
100
4.95
5.15
V
mA
V
W
mV
V
V
mA
VIN
5.5
28
V
(VIN = 12 V, Vout = 5.0 V, TA = +25°C for typical value; 0°C < TA < 85°C for min/max values unless noted otherwise)
Symbol
Test Conditions
Min
Typ
Max
Units
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