Product Specification
PE4257
Product Description
The PE4257 is a high-isolation UltraCMOS™ Switch designed
for wireless applications, covering a broad frequency range
from near DC up to 3000 MHz. This single-supply SPDT
switch integrates a two-pin CMOS control interface. It also
provides low insertion loss with extremely low bias
requirements while operating on a single 3-volt supply. In a
typical wireless application, the PE4257 provides
unprecedented isolation and integration.
The PE4257 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Figure 1. Functional Diagram
RFC
50
Ω
SPDT Absorptive UltraCMOS™
DC – 3.0 GHz RF Switch
Features
•
50
Ω
characteristic impedance
•
Integrated 50
Ω
0.25 watt terminations
•
High input IP3 > +55 dBm
•
High isolation 64 dB at 1000 MHz
•
Low insertion loss: typically 0.75 dB
at 1000 MHz and 0.95 dB at 2000 MHz
•
LV CMOS two-pin control
•
Single +3 volt supply operation
•
Low current consumption: 8
µA
Figure 2. Package Type
20-Lead 4x4 mm QFN
RF1
RF2
CMOS
Control
Driver
CTRL1 CTRL2
Table 1. Electrical Specifications @ +25 °C, V
DD
= 3.0 V
(Z
S
= Z
L
= 50
Ω)
Parameter
Operating Frequency
1
Insertion Loss
1000 MHz
2000 MHz
3000 MHz
1000 MHz
2000 MHz
3000 MHz
1000 MHz
2000 MHz
3000 MHz
5 MHz - 1000 MHz
5 MHz - 1000 MHz
1000 MHz
50% CTRL to 10 / 90 RF
5 MHz - 1000 MHz
50
29
61
46
40
57
54
42
Condition
Minimum
DC
Typical
0.75
0.95
1.2
64
50
44
63
60
48
80
55
31
2
Maximum
3000
0.95
1.15
1.4
Units
MHz
dB
Isolation Input to Output
dB
Isolation Output to Output
Input IP2
Input IP3
Input 1dB Compression
2
Switching Time
Video Feedthrough
3
dB
dBm
dBm
dBm
µs
15
mV
pp
Notes: 1. Device linearity will begin to degrade below 1 MHz.
2. Note Absolute Maximum ratings in Table 3.
3. Measured with a 1 ns risetime, 0/3 V pulse and 500 MHz bandwidth
Document No. 70-0166-03
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www.psemi.com
©2004-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 8
PE4257
Product Specification
Figure 3. Pin Configuration (Top View)
18 VSS/GND
CTRL1
19 GND
CTRL2
VDD
Table 3. Absolute Maximum Ratings
Symbol
V
DD
V
I
Parameter/Condition
Power supply voltage
Voltage on CTRL input
RF power on RFC, RF1, RF2
On Port/ Terminated Port
Storage temperature
Operating temperature
ESD voltage
(Human Body Model)
Min
-0.3
-0.3
Max
4.0
V
DD
+
0.3
33/24
Unit
V
V
dBm
°C
°C
V
20
17
16
GND
GND
RF1
GND, RF1 Term.
GND
1
GND
2
3
4
5
15 GND
14 GND
13
RF2
P
RF
T
ST
T
OP
V
ESD
-65
-40
1000
+150
+85
12 GND, RF2 Term.
11 GND
4x4mm 20-Lead QFN
Table 2. Pin Descriptions
No.
1
2
3
1
4
5
6
7
8
1
9
10
11
12
13
1
14
15
16
2
17
2
18
3
19
20
Pad
Notes:
1. RF pins 3, 8, and 13 must be at 0 VDC. The RF pins do not require DC
blocking capacitors for proper operation if the 0 VDC requirement is met.
2. Pins 16 and 17 are the CMOS controls that set the four operating states.
3. Connect pin 18 to GND to enable the negative voltage generator. Connect
pin 18 to V
SS
(-3 V) to bypass and disable internal -3 V supply generator. See
paragraph “Switching Frequency.”
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage.
Functional operation should be restricted to the
limits in the DC Electrical Specifications table.
Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Table 4. DC Electrical Specifications @ 25 °C
Parameter
V
DD
Power Supply
I
DD
Power Supply Current
(V
DD
= 3V, V
CNTL
= 3V)
Control Voltage High
Control Voltage Low
0.70 V
DD
0
0.30 V
DD
V
V
Name
GND
GND
RF1
GND
GND
GND
GND
RFC
GND
GND
GND
GND
RF2
GND
GND
CTRL2
CTRL1
VSS / GND
GND
VDD
GND
RF Ground
RF Ground
RF I/O
RF Ground
RF Ground
RF Ground
RF Ground
RF Common
RF Ground
RF Ground
RF Ground
RF Ground
RF I/O
RF Ground
RF Ground
Control 2
Control 1
Description
Min
2.7
GND 10
6
7
8
RFC
GND
GND
GND
9
Typ
3.0
8
Max
3.3
20
Unit
V
µA
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified.
Switching Frequency
The PE4257 has a maximum 25 kHz switching
rate when the internal negative voltage generator
is used (pin 18=GND). The rate at which the
PE4257 can be switched is only limited to the
switching time if an external -3 V supply is
provided at (pin18=V
SS
).
Document No. 70-0166-03
│
UltraCMOS™ RFIC Solutions
Negative Supply Option
Digital Ground
Supply
RF Ground Pad
©2004-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 8
PE4257
Product Specification
Table 5. Truth Table
CTRL1
Low
Low
High
High
Notes:
CTRL2
Low
High
Low
High
RFC – RF1
OFF
OFF
ON
N/A
1
RFC – RF2
OFF
ON
OFF
N/A
1
1. The operation of the PE4257 is not supported or characterized in the C1=V
DD
and C2=V
DD
state.
Document No. 70-0166-03
│
www.psemi.com
©2004-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 8
PE4257
Product Specification
Typical Performance Data @ 25°C (Unless Otherwise Noted)
(50-ohm impedance)
Figure 4. Insertion Loss – Input - Output
Figure 5. RF1 to RF2 Isolation
Figure 6. Isolation – RFC to RF1/RF2
Figure 7. Return Loss
©2004-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 8
Document No. 70-0166-03
│
UltraCMOS™ RFIC Solutions
PE4257
Product Specification
Evaluation Kit
The SPDT Switch Evaluation Kit board was designed to
ease customer evaluation of the PE4257 SPDT switch.
The RF common port is connected through a 50
Ω
transmission line to J2. Port 1 and Port 2 are
connected through 50
Ω
transmission lines to J1 and
J3. A through transmission line connects SMA
connectors J4 and J5. This transmission line can be
used to estimate the loss of the PCB over the
environmental conditions being evaluated.
The board is constructed of a four metal layer FR4
material with a total thickness of 0.031”. The
transmission lines were designed using a coplanar
waveguide with ground plane (28 mil core, 47.6 mil
width, 30mil gap).
Note the number of vias surrounding the device in the
layout shown in Figure 8. These vias are critical for
obtaining the specified isolation performance for the
device shown in this datasheet.
J6 provides a means for controlling DC and digital
inputs to the device. The provided jumpers short the
package pin to ground for logic low. When the jumper
is removed, the pin is pulled up to VDD for logic high.
When the jumper is in place, 3 µA of current will flow
through the 1 MΩ pull up resistor. This extra current
should not be attributed to the requirements of the
device.
Figure 8. Evaluation Board Layouts
Peregrine Specification 101/0151
Figure 9. Evaluation Board Schematic
Peregrine Specification 102/0198
Document No. 70-0166-03
│
www.psemi.com
©2004-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 8
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