MK3732-09
VCXO
AND
PLL
Description
The MK3732-09 series of devices includes the original
MK3732-09S and the new MK3732-09D. The
MK3732-09D is a drop-in replacement for the
MK3732-09S device. Compared to the earlier device,
the MK3732-09D offers improved power supply noise
rejection, expanded pull range, and lower gain.
The MK3732-09 is a low cost, low jitter, high
performance VCXO and PLL clock synthesizer
designed to replace expensive discrete VCXOs and
multipliers. The patented on-chip Voltage Controlled
Crystal Oscillator accepts a 0 to 3.3 V input voltage to
cause the output clocks to vary by ±115 ppm. Using
ICS’ analog/digital Phase-Locked Loop (PLL)
techniques, the device uses an inexpensive 27 MHz
pullable crystal input to produce three output clocks.
ICS manufactures the largest variety of MPEG clock
synthesizers for all applications. Consult ICS to
eliminate VCXOs, crystals, and oscillators from your
board.
The frequency of the on-chip VCXO is adjusted by an
external control voltage input into pin VIN. Because
VIN is a high impedance input, it can be driven directly
from an PWM RC integrator circuit.
Features
•
MK3732-09D is a drop-in replacement for the earlier
MK3732-09S device
•
•
•
•
Packaged in 16 pin SOIC
Replaces a VCXO and oscillator
Operating voltage of 3.3 V
Provides output of 27 MHz plus audio or modem
clock
•
Uses an inexpensive 27 MHz pullable crystal
•
On-chip patented VCXO with pull range of 200ppm
(minimum)
•
VCXO tuning voltage of 0 to 3.3 V
•
Advanced, low power, sub-micron CMOS process
MK3732-09D is Recommended for New Designs
Block Diagram
VDD
3
S 2 :S 0
V IN
X1
27 MHz
P u lla b le
C ry sta l
3
P L L /C lo c k
S y n th e s is
C irc u itry
CLK2
CLK3
1 3 .5 M H z o r o ff
X2
V o lta g e
C o n tro lle d
C ry s ta l
O s c illa to r
3
/2
CLK1
27MHz
GND
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MK3732-09
VCXO
AND
PLL
Pin Assignment
Clock Select Table
S2 S1 S0 Input
CLK1
REF/12
REF/16
REF
REF
REF
REF
REF
REF
CLK2
OFF
OFF
11.0592
11.0592
14.7456
12.288
24.576
18.432
CLK3
OFF
OFF
REF/2
REF/2
OFF
OFF
OFF
OFF
X1
VD D
VD D
VIN
GND
GND
GND
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X2
NC
S1
VDD
C LK1
C LK2
S0
C LK3
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
27
27
27
27
27
27
27
27
M K 3732-09D
M K 3732-09S
16 Pin (150 m il) S O IC
Pin Descriptions
Pin
Number
1
2
3
4
5,6,7
8
9
10
11
12
13
14
15
16
Pin
Name
XI
VDD
VDD
VIN
GND
S2
CLK3
S0
CLK2
CLK1
VDD
S1
NC
X2
Pin
Type
Input
Power
Power
Input
Power
Input
Output
Input
Output
Output
Power
Input
--
Input
Pin Description
Crystal connection. Connect to the external pullable crystal.
Connect to +3.3 V (0.01uf decoupling capacitor recommended)
Connect to +3.3 V (0.01uf decoupling capacitor recommended)
Voltage input to VCXO. Zero to 3.3V signal which controls the VCXO
frequency.
Connect to ground.
Select input #2. Selects outputs per table above.
Clock output #3 per table above.
Select #0. Selects outputs per table above.
Clock output #2 per table above.
Clock output #1 per table above.
Power supply. Connect to +3.3V.
Select input #1. Selects outputs per table above.
No connect. Do not connect anything to this pin.
Crystal connection. Connect to the external pullable crystal.
MDS 3732-09 C
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MK3732-09
VCXO
AND
PLL
External Component Selection
The MK3732-09 requires a minimum number of
external components for proper operation.
Decoupling Capacitors
Decoupling capacitors of 0.01µF should be connected
between VDD and GND on pins 2 and 5 and pins 3 and
6, as close to the MK3732-09 as possible. For optimum
device performance, the decoupling capacitors should
be mounted on the component side of the PCB. Avoid
the use of vias in the decoupling circuit.
The external crystal must be connected as close to the
chip as possible and should be on the same side of the
PCB as the MK3732-09. There should be no via’s
between the crystal pins and the X1 and X2 device
pins. There should be no signal traces underneath or
close to the crystal. See application note MAN05.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. Stuffing of these capacitors
on the PCB is optional. The need for these capacitors
is determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture
and frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
To determine the need for and value of the crystal
adjustment capacitors, you will need a PC board of
your final layout, a frequency counter capable of about
1 ppm resolution and accuracy, two power supplies,
and some samples of the crystals which you plan to
use in production, along with measured initial accuracy
for each crystal at the specified crystal load
capacitance, CL.
To determine the value of the crystal capacitors:
1. Connect VDD of the MK3732-09 to 3.3V. Connect
pin 3 of the MK3732-09 to the second power supply.
Adjust the voltage on pin 3 to 0V. Measure and record
the frequency of the CLK output.
2. Adjust the voltage on pin 3 to 3.3V. Measure and
record the frequency of the same output.
To calculate the centering error:
6
(
f
3.3
(
3.0
)V
–
f
t arg et
)
+
(
f
0V
–
f
t arg et
)
Error = 10 x ----------------------------------------------------------------------------------------
–
error
xtal
f
t arg et
Series Termination Resistor
When the PCB traces between the clock outputs (CLK,
pin 5) and the loads are over 1 inch, series termination
should be used. To series terminate a 50Ω trace (a
commonly used trace impedance) place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
Quartz Crystal
The MK3732-09 VCXO function consists of the
external crystal and the integrated VCXO oscillator
circuit. To assure the best system performance
(frequency pull range) and reliability, a crystal device
with the recommended parameters (shown below)
must be used, and the layout guidelines discussed in
the following section must be followed.
The frequency of oscillation of a quartz crystal is
determined by its “cut” and by the load capacitors
connected to it. The MK3732-09 incorporates on-chip
variable load capacitors that “pull” (change) the
frequency of the crystal. The crystal specified for use
with the MK3732-09 is designed to have zero
frequency error when the total of on-chip + stray
capacitance is 14pF.
Recommended Crystal Parameters:
Initial Accuracy at 25
°
C
Temperature Stability
Aging
Load Capacitance
Shunt Capacitance, C0
C0/C1 Ratio
Equivalent Series Resistance
Where:
f
target
= nominal crystal frequency
error
xtal
=actual initial accuracy (in ppm) of the crystal
being measured
If the centering error is less than ±25 ppm, no
adjustment is needed. If the centering error is more
than 25ppm negative, the PC board has excessive
stray capacitance and a new PCB layout should be
considered to reduce stray capacitance. (Alternately,
the crystal may be re-specified to a higher load
Revision 091801
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±20 ppm
±30 ppm
±20 ppm
14 pf
7 pF Max
250 Max
35
Ω
Max
MDS 3732-09 C
Int egrat ed C ircuit Syste ms
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MK3732-09
VCXO
AND
PLL
capacitance. Contact ICS for details.) If the centering
error is more than 25ppm positive, add identical fixed
centering capacitors from each crystal pin to ground.
The value for each of these caps (in pF) is given by:
External Capacitor =
2 x (centering error)/(trim sensitivity)
Trim sensitivity is a parameter which can be supplied
by your crystal vendor. If you do not know the value,
assume it is 30 ppm/pF. After any changes, repeat the
measurement to verify that the remaining error is
acceptably low (typically less than ±25ppm).
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK3732-09. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Soldering Temperature
7V
Rating
-0.5V to VDD+0.5V
0 to +70°C
-65 to +150°C
260°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Reference crystal parameters
Min.
0
+3.15
Typ.
–
Max.
+70
+3.45
Units
°C
V
Refer to page 3
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MK3732-09
VCXO
AND
PLL
DC Electrical Characteristics
VDD=3.3V ±5%
, Ambient temperature 0 to +70°C, unless stated otherwise
Parameter
Operating Voltage
Output High Voltage
Output Low Voltage
Output High Voltage (CMOS
Level)
Input High Voltage (S1:S0)
Input High Voltage (S2)
Input Low Voltage (S1:S0)
Input Low Voltage (S2)
Operating Supply Current
Short Circuit Current
VIN, VCXO Control Voltage
Symbol
VDD
V
OH
V
OL
V
OH
V
IH
V
IH
V
IL
V
IL
IDD
I
OS
V
IA
Conditions
I
OH
= -12 mA
I
OL
= 12 mA
I
OH
= -4 mA
Min.
3.15
2.4
Typ.
Max.
3.45
0.4
Units
V
V
V
V
V
V
VDD-0.4
2.0
2.5
0.8
0.5
V
V
mA
mA
No load
0
11
±50
3.3
V
AC Electrical Characteristics
VDD = 3.3V ±5%
, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Crystal Pullability
MK3732-09D
MK3732-09S
VCXO Gain
MK3732-09D
MK3732-09S
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
Maximum Output Jitter,
short term
t
OR
t
OF
t
D
t
J
VIN = VDD/2 + 1V, Note 1
VIN = VDD/2 + 1V, Note 1
0.8 to 2.0V, C
L
=15pF
2.0 to 0.8V, C
L
=15pF
Measured at 1.4V, C
L
=15pF
C
L
=15pF
40
50
400
100
120
1.5
1.5
60
ppm/V
ppm/V
ns
ns
%
ps
F
P
F
P
0V< VIN < 3.3V, Note 1
0V< VIN < 3.3V, Note 1
+ 115
+ 100
ppm
ppm
Symbol
Conditions
Min.
Typ.
Max. Units
Note 1: External crystal device must conform with Pullable Crystal Specifications listed on page 3.
MDS 3732-09 C
Int egrat ed C ircuit Syste ms
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