INTEGRATED CIRCUITS
DATA SHEET
UMA1002
Data processor for cellular radio
(DPROC2)
Product specification
Supersedes data of 1996 Sep 13
File under Integrated Circuits, IC17
1997 Jan 28
Philips Semiconductors
Product specification
Data processor for cellular radio
(DPROC2)
FEATURES
•
Single chip solution to all the data handling and
supervisory functions
•
Configuration to both AMPS and TACS
•
Additional JTACS option
•
I
2
C-bus serial control
•
All analog interface and filtering functions fully
implemented on chip
•
Error handling in hardware reduces software
requirements
•
Robust SAT decoding and transponding circuitry
•
Low current consumption by on-chip power-down
modes
•
Reduced system current consumption by new
integrated power-saving features
– Majority voting includes more intelligence
– On-chip control filler word filter
– BCH error filter
– Possibility to program ESCC bits
•
Small physical size: SO28 or LQFP32
•
External peripheral component count reduced
– On-chip selectable clock divider
– Integrated pull-up resistor at TXLINE
•
Simplified reset and abort software routines possible
•
The SO28 version is fully compatible with UMA1000LT
and UMF1000T.
QUICK REFERENCE DATA
SYMBOL
V
DD
I
DD
T
amb
supply voltage
supply current normal operation with external clock
operating ambient temperature
PARAMETER
−
−30
MIN.
2.7
TYP.
3.0
1.3
−
GENERAL DESCRIPTION
UMA1002
The UMA1002 is a low power CMOS LSI device
incorporating the data transceiving, data processing, and
SAT functions (including on-chip filtering) for an AMPS or
TACS hand-held portable cellular radio telephone.
In this data sheet, the UMA1002 is often referred to by the
descriptive term ‘DPROC2’.
MAX.
5.5
1.8
+70
V
UNIT
mA
°C
ORDERING INFORMATION
TYPE
NUMBER
UMA1002T
UMA1002H
PACKAGE
NAME
SO28
LQFP32
DESCRIPTION
plastic small outline package; 28 leads; body width 7.5 mm
plastic low profile quad flat package; 32 leads; body 7
×
7
×
1.4 mm
VERSION
SOT136-1
SOT358-1
1997 Jan 28
2
book, full pagewidth
1997 Jan 28
VDDA
INVRX RECDATA
MVO
VDDD
(28)
RXLINE
RXCLK
COMPARATOR 1
DATA
RECOVERY
ERROR
CORECTION
19 (17)
5 (1)
BUSY/VSAT
RACTRL
SYNCRONIZATION
AND VOTING
27 (26)
28 (27)
7 (4)
10 (8)
(3)
8 (5)
INTERPOLATOR
COMPARATOR 2
ARBITRATION
LOGIC
SAT
REGENERATION
SAT
DETERMINATION
11 (9)
18 (16)
OUTPUT
FILTER
ST
GENERATOR
17 (15)
TRANSMIT
BUFFER
15 (13)
MANCHESTER
AND BCH
ENCODING
TACTRL
TXCLK
TXHOLD
TXLINE
25 (25)
TEST
LOGIC
GATED D/A
I
2
C
INTERFACE
24 (24)
SDA
(6)
JTACS
21 (21)
INVTX
A0
23
(23)
SCL
SAT
RECOVERY
DOTTING
DETECTOR
20 (19)
TXCTRL
BLOCK DIAGRAM
Philips Semiconductors
3
DEMODD
(31)
ANTI-
ALIASING
FILTER
Data processor for cellular radio
(DPROC2)
SAT
FILTER
UMA1002
BIAS
GENERATOR
GATED D/A
2 (30)
AGND
3
9
(7)
1 (29)
VSSA
VSSD
14 (12)
TST TSCAN
22
(22)
4
DATA
(32)
CLOCK
FILTER
6
RESET
(2)
RESET, CLOCK AND
POWER-DOWN
GENERATOR
(20)
12 (10)
13 (11)
MBD827
CLKSEL
CLKIN
CLKOUT
Pins in parenthesis apply to UMA1002H in LQFP32.
Product specification
UMA1002
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Data processor for cellular radio
(DPROC2)
PINNING
PIN
SYMBOL
SO28
V
SSA
AGND
DEMODD
DATA
1
2
3
4
LQFP32
29
30
31
32
DESCRIPTION
UMA1002
Negative analog supply (0 V). To be connected low-ohmic to V
SSD
.
Internally generated analog signal ground. Voltage level =
1
⁄
2
V
DDA
. This pin should
be connected to a blocking capacitor, no DC load allowed.
DEMODD inputs analog data and SAT signals from the RF demodulator. This pin
should normally be AC-coupled. See Chapter “AC characteristics”.
Data is an analog output which provides the Manchester encoded and filtered data
signal, SAT and signalling tone. This signal should normally be AC-coupled into the
Audio/Data summer. See Chapter “AC characteristics”.
Received audio control output. Open-drain output used to blank the audio path to
the earpiece when a sequence of dotting followed by a synchronization word or 2
synchronization words separated by 77 bits is detected. RACTRL and TACTRL
functions can be combined using one line. Output level LOW means audio muted.
Master reset input resetting all internal flip-flops to the specified state. This input
has no influence on analog parts, but must be controlled by an active HIGH
microcontroller port.
This input inverts the sense of received data stream, which allows RF
demodulators with high or low local oscillators to be used. The AMPS and TACS
specifications define NRZ encoded logic 1 as a LOW-to-HIGH transition in the
centre of a data bit period. The polarity of the demodulated data stream into
DPROC2 depends on the receiver local oscillator. Input LOW means data normal.
Received data signal output to the system controller.
Test input pin (note 1).
Output of the recovered digital data signal (note 1).
Transmitter audio control output. This open-drain output is used to blank the audio
path and enable the data path to the modulator during data bursts on the RVC.
Output level LOW means audio muted.
1.2 MHz or 9.6 MHz external master clock input. This input signal should be
accurate to 100
×
10
−6
and have a worst case 60 : 40 mark-space ratio.
Output of 1.2 MHz clock signal (for APROC) derived from CLKIN.
Negative digital supply (0 V), internally connected to substrate. To be connected
low-ohmic to V
SSA
.
Open-drain bidirectional data line to the system controller (internal 100 kΩ pull-up).
Not connected.
This input holds off transmission of data when set to HIGH.
Transmitted data clock input from the system controller.
Output indicating the status of the RECC by providing output information based on
a majority decision on the last 3 consecutive Busy/Idle bits (FVC = logic 0). Output
level LOW means channel idle.
Indicating the result of the comparison of the measured SAT and the expected SAT
colour-code bits (I
2
C-bus register) in the voice channel mode (FVC = logic 1 and
ENSM = logic 1). Output level LOW means incoming SAT not equal to expected
SAT.
RACTRL
5
1
RESET
6
2
INVRX
7
4
RXLINE
TST
RECDATA
TACTRL
8
9
10
11
5
7
8
9
CLKIN
CLKOUT
V
SSD
TXLINE
n.c.
TXHOLD
TXCLK
BUSY/VSAT
12
13
14
15
16
17
18
19
10
11
12
13
14
15
16
17
1997 Jan 28
4
Philips Semiconductors
Product specification
Data processor for cellular radio
(DPROC2)
PIN
SYMBOL
SO28
TXCTRL
INVTX
20
21
LQFP32
19
21
DESCRIPTION
UMA1002
Transmitter control open-drain output used to disable the transmitter during an
RECC access failure. Output level LOW means RF disabled.
This input inverts the sense of transmitted data stream, which allows RF
modulators with high or low local oscillators to be used. The AMPS and TACS
specifications define NRZ encoded logic 1 as a LOW-to-HIGH transition in the
centre of a data bit period. The polarity of the modulated data stream depends on
the transmitter local oscillator. Input LOW means data inverted.
Test switch input, only enabled if TST = logic 1, but should have a defined state.
Input to select the least significant bit of the I
2
C-bus address.
Serial data input/output (I
2
C-bus).
Serial clock input (I
2
C-bus).
Not connected.
Received data clock input from the system controller.
Digital supply voltage (+3 V).
Analog supply voltage (+3 V).
Majority voting output indicating that on FOCC the first 3 received words do not
differ from each other and thus the majority decision over 5 words can already be
carried out. Because of the required speed, indication is at this pin (and not via the
I
2
C-bus) which can be monitored by the system controller. Output LOW means the
receiver can be switched off.
Digital input signal for JTACS, input HIGH means that data is routed from TXLINE
directly without processing to gated D/A converter (if enabled by STEN bit).
Input switch for internal divide-by-8 or divide-by-1 divider between CLKIN and
CLKOUT (internal pull-down
→
divide-by-1 is default if not bonded out in SO28
package).
TSCAN
A0
SDA
SCL
n.c.
RXCLK
V
DDD
V
DDA
MVO
22
23
24
25
26
27
28
−
−
22
23
24
25
18
26
27
28
3
JTACS
CLKSEL
−
−
6
20
Note
1. Must not be connected in existing applications.
1997 Jan 28
5
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