Philips Semiconductors
Product specification
Low-power dual frequency synthesizer
for radio communications
FEATURES
•
Two fully programmable RF dividers up to 1.1 GHz
•
Fully programmable reference divider up to 35 MHz
•
2 : 1 or 1 : 1 ratio of selectable reference frequencies
•
Fast three-line serial bus interface
•
Adjustable phase comparator gain
•
Programmable out-of-lock indication for both loops
•
On-chip voltage doubler
•
Low current consumption from 3 V supply
•
Separate power-down mode for each synthesizer
•
Up to 4 open-drain output ports.
APPLICATIONS
•
Cordless telephone
•
Hand-held mobile radio.
QUICK REFERENCE DATA
SYMBOL
V
DD1
, V
DD2
V
CC
V
CCvd
I
DDO1
+I
DDO2
+
I
CCO
I
DD1pd
+ I
DD2pd
+ I
CCpd
I
DD1pd
f
RFA
, f
RFB
f
XTALIN
f
pc(min)
f
pc(max)
T
amb
PARAMETER
digital supply voltage
charge pump supply
voltage
charge pump supply from
voltage doubler
operating supply current
current in power-down
mode per supply
current in power-down
mode from supply V
DD
RF input frequency for
each synthesizer
crystal input frequency
minimum phase
comparator frequency
maximum phase
comparator frequency
operating ambient
temperature
f
RF
= 50 to 1100 MHz;
f
XTALIN
= 3 to 35 MHz
f
RF
= 50 to 1100 MHz;
f
XTALIN
= 3 to 35 MHz
synthesizer A
2.6 V
≤
V
DD
≤
5.5 V
synthesizer B
2.6 V
≤
V
DD
≤
4.5 V
synthesizer B
2.6 V
≤
V
DD
≤
5.0 V
CONDITIONS
V
DD1
= V
DD2
external supply; doubler
disabled; V
CC
≥
V
DD
doubler enabled
both synthesizers ON; doubler
disabled; V
DD1
= V
DD2
= 5.5 V
doubler disabled;
V
DD1
= V
DD2
= 5.5 V
doubler enabled;
V
DD1
= V
DD2
= 3 V
MIN.
2.6
2.6
−
−
−
−
50
3
−
−
−30
−30
0
−
−
TYP.
GENERAL DESCRIPTION
UMA1015M
The UMA1015M is a low-power dual frequency
synthesizer for radio communications which operates in
the 50 to 1100 MHz frequency range. Each synthesizer
consists of a fully programmable main divider, a phase and
frequency detector and a charge pump. There is a fully
programmable reference divider common to both
synthesizers which operates up to 35 MHz. The device is
programmed via a 3-wire serial bus which operates up to
10 MHz. The charge pump currents (gains) are fixed by an
external resistance at pin 20 (I
SET
). The BiCMOS device is
designed to operate from 2.6 V (3 Ni-Cd cells) to 5.5 V at
low current. Digital supplies V
DD1
and V
DD2
must be at the
same potential. The charge pump supply (V
CC
) can be
provided by an external source or on-chip voltage doubler.
V
CC
must be equal to or higher than V
DD1
. Each
synthesizer can be powered-down independently via the
serial bus to save current. It is also possible to power-down
the device via the HPD input (pin 5).
MAX.
5.5
6.0
6.0
−
−
−
1100
35
−
−
+85
+85
+85
UNIT
V
V
V
mA
mA
mA
MHz
MHz
kHz
kHz
°C
°C
°C
2V
DD1
−
0.6
9.6
0.01
0.15
−
−
10
750
−
−
−
1995 Jun 22
2
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer
for radio communications
PINNING
SYMBOL
P1
P2
CPA
V
DD1
HPD
RFA
DGND
f
XTALIN
P3
f
XTALO
CLK
DATA
E
V
DD2
RFB
AGND
CPB
V
CC
P0/OOL
I
SET
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DESCRIPTION
output Port 1
output Port 2
charge-pump output synthesizer A
digital supply voltage 1
hardware power-down
(input LOW = power-down)
RF input synthesizer A
digital ground
common crystal frequency input from
TCXO
output Port 3
open-drain output of f
XTAL
signal
programming bus clock input
programming bus data input
programming bus enable input
(active LOW)
digital supply voltage 2
RF input synthesizer B
analog ground to charge pumps
charge pump output synthesizer B
analog supply to charge pump;
external or voltage doubler output
Port output 0/out-of-lock output
regulator pin to set charge-pump
currents
UMA1015M
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
Main dividers
Each synthesizer has a fully programmable 17-bit main
divider. The RF input drives a pre-amplifier to provide the
clock to the first divider bit. The pre-amplifier has a high
input impedance, dominated by pin and pad capacitance.
The circuit operates with signal levels from below
50 mV (RMS) up to 250 mV (RMS), and at frequencies up
to 1.1 GHz. The high frequency sections of the divider are
implemented using bipolar transistors, while the slower
section uses CMOS technology. The range of division
ratios is 512 to 131071.
Reference divider
There is a common fully programmable 12-bit reference
divider for the two synthesizers. The input f
XTALIN
drives a
1995 Jun 22
4
pre-amplifier to provide the clock input for the reference
divider. This clock signal is also buffered and output on pin
f
XTALO
(open drain). An extra divide-by-2 block allows a
reference comparison frequency for synthesizer B to be
half that of synthesizer A. This feature is selectable using
the program bit SR. If the programmed reference divider
ratio is R then the ratio for each synthesizer is as given in
Table 1.
The range for the division ratio R is 8 to 4095. Opposite
edges of the divider output are used to drive the phase
detectors to ensure that active edges arrive at the phase
detectors of each synthesizer at different times. This
minimizes the potential for interference between the
charge pumps of each loop. The reference divider consists
of CMOS devices operating beyond 35 MHz.
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer
for radio communications
Table 1
SR
0
1
Phase comparators
For each synthesizer, the outputs of the main and
reference dividers drive a phase comparator where a
charge pump produces phase error current pulses for
integration in an external loop filter. The charge pump
current is set by an external resistance R
SET
at pin I
SET
,
where a temperature-independent voltage of 1.2 V is
generated. R
SET
should be between 12 kΩ and 60 kΩ (to
give an I
SET
of 100
µA
and 20
µA
respectively).
The charge-pump current, I
CP
, can be programmed to be
either (12
×
I
SET
) or (24
×
I
SET
) with the maximum being
2.4 mA. The dead zone, caused by finite switching of
current pulses, is cancelled by an internal delay in the
phase detector thus giving improved linearity. The charge
pump has a separate supply, V
CC
, which helps to reduce
the interference on the charge pump output from other
parts of the circuit. Also, V
CC
can be higher than V
DD1
if a
wider range on the VCO input is required. V
CC
must not be
less than V
DD1
.
Voltage doubler
If required, there is a voltage doubler on-chip to supply the
charge pumps at a higher level than the nominal available
supply. The doubler operates from the digital supply V
DD1
,
and is internally limited to a maximum output of 6 V.
An external capacitor is required on pin V
CC
for smoothing,
the capacitor required to develop the extra voltage is
integrated on-chip. To minimize the noise being introduced
to the charge pump output from the voltage doubler, the
doubler clock is suppressed (provided both loops are
in-lock) for the short time that the charge pumps are active.
The doubler clock (RF/64) is derived from whichever main
divider is operating (synthesizer A has priority). While both
synthesizers are powered down (and the doubler is
enabled), the doubler clock is supplied by a low-current
internal oscillator. The doubler can be disabled by
programming the bit VDON to logic 0, in order to allow an
external charge pump supply to be used.
Out-of-lock indication/output ports
There is a lock detector on-chip for each synthesizer. The
lock condition of each, or both loops, is output via an
open-drain transistor which drives the pin P0/OOL (when
out-of-lock, the transistor is turned on and therefore the
Synthesizer ratio of reference divider
SYNTHESIZER A
R
R
SYNTHESIZER B
R
2R
UMA1015M
output is forced LOW). The lock condition output is
software selectable (see Table 4). An out-of-lock condition
is flagged when the phase error is greater than T
00L
, the
value of which is approximately equal to 80 cycles of the
relevant RF input. The out-of-lock flag is only released
after 8 consecutive reference cycles where the phase error
is less than T
00L
. The out-of-lock function can be disabled,
via the serial bus, and the pin P0/OOL can be used as an
output port. Three other port outputs P1, P2 and P3
(open-drain transistors) are also available.
Serial programming bus
A simple 3-line unidirectional serial bus is used to program
the circuit. The 3 lines are DATA, CLK and E (enable). The
data sent to the device is loaded in bursts framed by E.
Programming clock edges are ignored until E goes active
LOW. The programmed information is loaded into the
addressed latch when E returns inactive HIGH. This is
allowed when CLK is in either state without causing any
consequences to the register data. Only the last 21 bits
serially clocked into the device are retained within the
programming register. Additional leading bits are ignored,
and no check is made on the number of clock pulses. The
fully static CMOS design uses virtually no current when the
bus is inactive. It can always capture new programming
data even during power-down of both synthesizers.
However when either synthesizer A or synthesizer B or
both are powered-on, the presence of a TCXO signal is
required at pin 8 (f
XTALIN
) for correct programming.
Data format
Data is entered with the most significant bit first. The
leading bits make up the data field, while the trailing four
bits are an address field. The address bits are decoded on
the rising edge of E. This produces an internal load pulse
to store the data in the addressed latch. To ensure that
data is correctly loaded on first power-up, E should be held
LOW and only taken HIGH after having programmed an
appropriate register. To avoid erroneous divider ratios, the
pulse is inhibited during the period when data is read by
the frequency dividers. This condition is guaranteed by
respecting a minimum E pulse width after data transfer.
The data format and register bit allocations are shown in
Table 2.
1995 Jun 22
5
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