INTEGRATED CIRCUITS
DATA SHEET
UMA1020M
Low-voltage dual frequency
synthesizer for radio telephones
Product specification
Supersedes data of November 1994
File under Integrated Circuits, IC03
1995 Jun 15
Philips Semiconductors
Product specification
Low-voltage dual frequency
synthesizer for radio telephones
FEATURES
•
Low current from 3 V supply
•
Fully programmable RF divider
•
3-line serial interface bus
•
Second synthesizer to control first IF or offset loop
frequency
•
Independent fully programmable reference dividers for
each loop, driven from external crystal oscillator
•
Dual phase detector outputs to allow fast frequency
switching
•
Integrated digital-to-analog converter
•
Dual power-down modes.
APPLICATIONS
•
2 GHz mobile telephones
•
Portable battery-powered radio equipment.
GENERAL DESCRIPTION
The UMA1020M BICMOS device integrates prescalers,
programmable dividers, and phase comparators to
implement two phase-locked loops. The device is
designed to operate from 3 NiCd cells, in pocket phones,
with low current and nominal 5 V supplies.
QUICK REFERENCE DATA
SYMBOL
V
CC
, V
DD
I
CC
+ I
DD
PARAMETER
supply voltage
principal synthesizer supply current
principal and auxiliary synthesizer
supply current
I
CCPD
, I
DDPD
current in power-down mode per supply
f
VCO
f
AI
f
XTAL
f
PPC
f
APC
T
amb
principal input frequency
auxiliary input frequency
crystal reference input frequency
principal phase comparator frequency
auxiliary phase comparator frequency
operating ambient temperature
CONDITIONS
V
CC
≥
V
DD
auxiliary synthesizer in
power-down mode
principal and auxiliary
synthesizers ON
−
−
−
1700
20
3
−
−
−30
MIN.
2.7
−
9.4
12.1
12
−
−
−
200
200
−
UMA1020M
The principal synthesizer operates at RF input frequencies
up to 2.4 GHz the auxiliary synthesizer operates at
300 MHz. The auxiliary loop is intended for the first IF or to
transmit offset loop-frequency settings. Each synthesizer
has a fully programmable reference divider. All divider
ratios are supplied via a 3-wire serial programming bus.
Separate power and ground pins are provided to the
analog and digital circuits. The ground leads should be
externally short-circuited to prevent large currents flowing
across the die and thus causing damage. Digital supplies
V
DD1
and V
DD2
must also be at the same potential. V
CC
must be equal to or greater than V
DD
(i.e. V
DD
= 3 V and
V
CC
= 5 V for wider tuning range).
The principal synthesizer phase detector uses two charge
pumps, one provides normal loop feedback, while the
other is only active during fast mode to speed-up
switching. The auxiliary loop has a separate phase
detector. All charge pump currents (gain) are fixed by an
external resistance at pin I
SET
(pin 14). Only passive loop
filters are used; the charge-pumps function within a wide
voltage compliance range to improve the overall system
performance. An on-chip 7-bit DAC enables adjustment of
an external function, such as the temperature
compensation of a crystal oscillator.
TYP.
MAX.
5.5
−
−
−
2400
300
40
−
−
+85
UNIT
V
mA
mA
µA
MHz
MHz
MHz
kHz
kHz
°C
1995 Jun 15
2
Philips Semiconductors
Product specification
Low-voltage dual frequency
synthesizer for radio telephones
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
UMA1020M
BLOCK DIAGRAM
SSOP20
DESCRIPTION
UMA1020M
VERSION
SOT266-1
plastic shrink small outline package; 20 leads; body width 4.4 mm
Fig.1 Block diagram.
1995 Jun 15
3
Philips Semiconductors
Product specification
Low-voltage dual frequency
synthesizer for radio telephones
PINNING
SYMBOL
FAST
CPPF
CPP
V
DD1
V
DD2
PRI
DGND
f
XTAL
POFF
DOUT
CLK
DATA
E
I
SET
AUX
AGND
CPA
V
CC
AOFF
LOCK
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DESCRIPTION
control input to speed-up main
synthesizer
principal synthesizer speed-up
charge-pump output
principal synthesizer normal
charge-pump output
digital power supply 1
digital power supply 2
2 GHz principal synthesizer
frequency input
digital ground
crystal frequency input from TCXO
principal synthesizer power-down
input
7-bit digital-to-analog output
programming bus clock input
programming bus data input
programming bus enable input
(active LOW)
regulator pin to set the charge-pump
currents
auxiliary synthesizer frequency input
analog ground
auxiliary synthesizer charge-pump
output
supply for charge-pump and DAC
circuits
auxiliary synthesizer power-down
input
in-lock detect output (main PLL); test
mode output
UMA1020M
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
Principal synthesizer
Programmable reference and main dividers drive the
principal PLL phase detector. Two charge pumps produce
phase error current pulses for integration in an external
loop filter. A hardwired power-down input POFF (pin 9)
ensures that the dividers and phase comparator circuits
can be disabled.
The PRI input (pin 6) drives a preamplifier to provide the
clock to the first divider stage. The preamplifier has a high
input impedance, dominated by pin and pad capacitance.
The circuit operates with signal levels from 60 mV to
180 mV (RMS), and at frequencies up to 2.4 GHz. The
high frequency divider circuits use bipolar transistors,
slower bits are CMOS. Divide ratios (512 to 131071) allow
a 2 MHz phase comparison frequency.
1995 Jun 15
4
Philips Semiconductors
Product specification
Low-voltage dual frequency
synthesizer for radio telephones
The reference and main divider outputs are connected to
a phase/frequency detector that controls two charge
pumps. The two pumps have a common bias setting
current that is set by an external resistance. The ratio
between currents in fast and normal operating modes can
be programmed via the 3-wire serial bus. The low current
pump remains active except in power-down. The high
current pump is enabled via the control input FAST (pin 1).
By appropriate connection to the loop filter, dual bandwidth
loops are provided: short time constant during frequency
switching (FAST mode) to speed-up channel changes and
low bandwidth in the settled state (on-frequency) to reduce
noise and breakthrough levels.
The principal synthesizer speed-up charge pump (CPPF)
is controlled by the FAST input in synchronization with
phase detector operation in such a way that potential
disturbances are minimized. The dead zone (caused by
finite time taken to switch the current sources on or off) is
cancelled by feedback from the normal pump output to the
phase detector thereby improving linearity.
An open drain transistor drives the output pin LOCK
(pin 20). It is recommended that the pull-up resistor from
this pin to V
DD
is chosen such that the value is high enough
to keep the sink current in the LOW state below 400
µA.
The circuit can be programmed to output either the phase
error in the principal or auxiliary phase detectors or the
combination from both detectors (OR function). The
resultant output will be a current pulse with the duration of
the selected phase error. By appropriate external filtering
and threshold comparison, an out-of-lock or an in-lock flag
is generated.
Auxiliary synthesizer
The auxiliary synthesizer has a 14-bit main divider and an
11-bit reference divider. A separate power-down input
AOFF (pin 19), disables currents in the auxiliary dividers,
phase detector, and charge pump. The auxiliary input
signal is amplified and fed to the main divider. The input
buffer presents a high impedance, dominated by pin and
pad capacitance. First divider stages use bipolar
technology operating at input frequencies up to 300 MHz;
the slower bits are CMOS. The auxiliary loop phase
detector and charge pump use similar circuits to the main
loop low-current phase comparator, including dead-zone
compensation feedback.
The auxiliary reference divider is clocked on the opposite
edge of the principal reference divider to ensure that active
edges arrive at the auxiliary and principal phase detectors
at different times. This minimizes the potential for
interference between the charge pumps of each loop.
Serial programming bus
UMA1020M
A simple 3-line unidirectional serial bus is used to program
the circuit. The 3 lines are DATA, CLK and E (enable). The
data sent to the device is loaded in bursts framed by E.
Programming clock edges and their appropriate data bits
are ignored until E goes active LOW. The programmed
information is loaded into the addressed latch when E
returns inactive HIGH. Only the last 21 bits serially clocked
into the device are retained within the programming
register. Additional leading bits are ignored, and no check
is made on the number of clock pulses. The fully static
CMOS design uses virtually no current when the bus is
inactive. It can always capture new programmed data
even during power-down of main and auxiliary loops.
However when either principal synthesizer or auxiliary
synthesizer or both are powered-on, the presence of a
TCXO signal is required at pin 8 (f
XTAL
) for correct
programming.
Data format
Data is entered with the most significant bit first. The
leading bits make up the data field, while the trailing four
bits are an address field. The UMA1020M uses 6 of the
16 available addresses. The data format is shown in
Table 1. The first entered bit is p1, the last bit is p21.
The trailing address bits are decoded on the inactive edge
of E. This produces an internal load pulse to store the data
in one of the addressed latches. To ensure that the data is
correctly loaded on first power-up, E should be held LOW
and only taken HIGH after having programmed an
appropriate register. To avoid erroneous divider ratios, the
pulse is not allowed during data reads by the frequency
dividers. This condition is guaranteed by respecting a
minimum E pulse width after data transfer. The
corresponding relationship between data fields and
addresses is given in Table 2.
1995 Jun 15
5
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