* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
DESCRIPTION
The WV3EG264M72ESFR is a 2x64Mx72 Double Data
Rate DDR SDRAM high density module. This memory
module consists of eighteen 64Mx8 bit with 4 banks DDR
Synchronous DRAMs in FBGA packages, mounted on a
200-pin SO-DIMM FR4 substrate.
OPERATING FREQUENCIES
DDR333@CL = 2.5
Clock Speed
CL-t
RCD
-t
RP
166MHz
2.5-3-3
DDR266@CL = 2
133MHz
2-2-2
DDR266@CL = 2.5
133MHz
2.5-3-3
August 2005
Rev. 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
PIN CONFIGURATION
Pin No.
Symbol
Pin No.
Symbol
Pin No.
Symbol
Pin No.
Symbol
WV3EG264M72ESFR-D4
ADVANCED
PIN NAMES
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
DQ42
DQ46
DQ43
DQ47
V
CC
V
CC
V
CC
NC
V
SS
NC
V
SS
V
SS
DQ48
DQ52
DQ49
DQ53
V
CC
V
CC
DQS6
DM6
DQ50
DQ54
V
SS
V
SS
DQ51
DQ55
DQ56
DQ60
V
CC
V
CC
DQ57
DQ61
DQS7
DM7
V
SS
V
SS
DQ58
DQ62
DQ59
DQ63
V
CC
V
CC
SDA
SA0
SCL
SA1
V
CCSPD
SA2
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
V
REF
V
REF
V
SS
V
SS
DQ0
DQ4
DQ1
DQ5
V
CC
V
CC
DQS0
DM0
DQ2
DQ6
V
SS
V
SS
DQ3
DQ7
DQ8
DQ12
V
CC
V
CC
DQ9
DQ13
DQS1
DM1
V
SS
V
SS
DQ10
DQ14
DQ11
DQ15
V
CC
V
CC
CK0
V
CC
CK0#
V
SS
V
SS
V
SS
DQ16
DQ20
DQ17
DQ21
V
CC
V
CC
DQS2
DM2
DQ18
DQ22
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
V
SS
V
SS
DQ19
DQ23
DQ24
DQ28
V
CC
V
CC
DQ25
DQ29
DQS3
DM3
V
SS
V
SS
DQ26
DQ30
DQ27
DQ31
V
CC
V
CC
CB0
CB4
CB1
CB5
V
SS
V
SS
DQS8
DM8
CB2
CB6
V
CC
V
CC
CB3
CB7
NC
RESET#
V
SS
V
SS
NC
V
SS
NC
V
CC
V
CC
V
CC
CKE1
CKE0
NC
NC
A12
A11
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
A9
A8
V
SS
V
SS
A7
A6
A5
A4
A3
A2
A1
A0
V
CC
V
CC
A10/AP
BA1
BA0
RAS#
WE#
CAS#
CS0#
CS1#
NC
NC
V
SS
V
SS
DQ32
DQ36
DQ33
DQ37
V
CC
V
CC
DQS4
DM4
DQ34
DQ38
V
SS
V
SS
DQ35
DQ39
DQ40
DQ44
V
CC
V
CC
DQ41
DQ45
DQS5
DM5
V
SS
V
SS
Pin Name
A0-A12
BA0, BA1
DQ0-DQ63
CB0-CB7
DQS0-DQS8
CK0,CK0#
CKE0, CKE1
CS0#, CS1#
RAS#
CAS#
WE#
V
CC
V
CCQ
V
SS
SA0-SA2
SDA
V
REF
DM0-DM8
V
CCSPD
SCL
RESET#
NC
Function
Address Inputs
SDRAM Bank Address
Data Input/Output
Check Bits
Data strobes
Clock inputs, positive/negative
Clock enable input
Chip select input
Row Address Strobe
Column Address Strobe
Write Enable
Core Power
I/O Power
Ground
EEPROM address
Serial Data Input/Output
Input/Output Reference
Data-in mask
Serial EEPROM power supply
Serial Presence Detect(SPD) Clock Input
Reset enable
Spare pins, No connect
August 2005
Rev. 0
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3EG264M72ESFR-D4
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
CS1#
CS0#
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
S0#
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
S1#
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
S0#
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
S1#
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
S0#
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
S1#
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
S0#
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
S1#
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
S0#
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
S1#
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
S0#
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
S1#
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS8
DM8
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
S0#
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
S1#
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
S0#
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
S1#
DM
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
CS# DQS
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
0
1
2
3
4
5
6
7
CS# DQS
Serial PD
SCL
WP
A0
A1
A2
SA1 SA2
SDA
120 Ohms
PLL
CK0
CK0#
CS0#
CS1#
BA0-BA1
A0-A12
RAS#
CAS#
CKE0
CKE1
WE#
PCK
PCK#
R
E
G
I
S
T
E
R
RCS0#
RCS1#
RBA0-RBA1
RA0-RA12
RRAS#
RCAS#
RCKE0
RCKE1
RWE#
RESET#
BA0-BA1:
DDR SDRAMs
A0-A12:
DDR SDRAMs
RAS#:
DDR SDRAMs
CAS#:
DDR SDRAMs
CKE:
DDR SDRAMs
CKE:
DDR SDRAMs
WE#:
DDR SDRAMs
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
REGISTER X 2
SPD
DDR SDRAMs
V
CCSPD
V
CCQ
/V
CC
V
REF
V
SS
DDR SDRAMs
DDR SDRAMs
NOTE: All resistor values are 22 ohms unless otherwise specified.
August 2005
Rev. 0
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
0°C T
A
70°C
Parameter
Supply voltage (for device with a nominal V
CC
of 2.5V)
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage (system)
Input logic high voltage
Input logic low voltage
Input Voltage Level, CK and CK# inputs
Input Differential Voltage, CK and CK# inputs
Input leakage current
Output leakage current
Output High Current(Normal strengh driver); V
OUT
= V
TT
+ 0.84V
Output High Current(Normal strengh driver); V
OUT
= V
TT
- 0.84V
Output High Current(Half strengh driver); V
OUT
= V
TT
+ 0.45V
Output High Current(Half strengh driver); V
OUT
= V
TT
- 0.45V
Symbol
V
CC
V
CCQ
V
REF
V
TT
V
IH
(DC)
V
IL
(DC)
V
IN
(DC)
V
ID
(DC)
I
I
I
OZ
I
OH
I
OL
I
OH
I
OL
Min
2.3
2.3
0.49*V
CCQ
V
REF
-0.04
V
REF
+0.15
-0.3
-0.3
0.3
-2
-5
-16.8
16.8
-9
9
WV3EG264M72ESFR-D4
ADVANCED
DC OPERATING CONDITIONS
Max
2.7
2.7
0.51*V
CCQ
V
REF
+0.04
V
CCQ
+0.3
V
REF
-0.15
V
CCQ
+0.3
V
CCQ
+0.6
2
5
Unit
V
V
V
V
V
V
V
uA
uA
mA
mA
mA
mA
Note
1
2
4
4
3
Notes:
1. Includes ± 25mV margin for DC offset on V
REF
, and a combined total of ± 50mV margin for all AC noise and DC offset on V
REF
, bandwidth limited to 20MHz. The DRAM must
accommodate DRAM current spikes on V
REF
and internal DRAM noise coupled to V
REF
, both of which may result in V
REF
noise. V
REF
should be de-coupled with an inductance of ≤ 3nH.
2. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set equal to V
REF
, and must track variations in the DC level of V
REF
3. V
ID
is the magnitude of the difference between the input level on CK and the input level on CK#.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative
to a V
REF
envelop that has been bandwidth limited to 200MHz.
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
CC
& V
CCQ
pin relative to V
SS
Storage Temperature
Operating Temperature
Power dissipation – 1GB single mezzanine memory
Short circuit current
Symbol
V
IN
, V
OUT
V
CC
, V
CCQ
T
STG
T
A
P
D
I
OS
Value
-0.5 ~ 3.3
-1.0 ~ 3.6
-55 ~ +150
0 ~ +70
18
50
Unit
V
V
°C
°C
W
mA
NOTE:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
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