The AS7C512 is a high performance CMOS 524,288-bit Static Random Access Memory (SRAM) organized as 65,536 words × 8 bits. It is
designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 12/15/20/25/35 ns with output enable access times (t
OE
) of 3/4/5/6/8 ns are ideal
for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank
memory systems.
When CE1 is HIGH or CE2 is LOW the device enters standby mode. The standard AS7C512 is guaranteed not to exceed 27.5 mW power
consumption in standby mode; the L version is guaranteed not to exceed 4.25 mW, and typically requires only 800
µW.
The L version also
offers 2.0V data retention, with maximum power of 400
µW.
A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0-I/O7 is written
on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external
devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) HIGH. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is
active, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply. The AS7C512 is packaged in all high volume
industry standard packages.
Absolute maximum ratings
Parameter
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Temperature under bias
DC output current
Symbol
V
t
P
D
T
stg
T
bias
I
out
Min
–0.5
–
–55
–10
–
Max
+7.0
1.0
+150
+85
20
Unit
V
W
o
C
o
C
mA
Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute max-
imum rating conditions for extended periods may affect reliability.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
