SDRAM
AS4SD4M16
4 Meg x 16 SDRAM
Synchronous DRAM Memory
FEATURES
• Full Military temp (-55°C to 125°C) processing available
• Copper lead frame option for enhanced reliability
• WRITE Recovery (
t
WR
/
t
DPL
)
t
WR
= 2 CLK
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8 or full page
• Auto Precharge and Auto Refresh Modes
• Self Refresh Mode (IT & ET)
• 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Longer lead TSOP for improved reliability (OCPL*)
PIN ASSIGNMENT
(Top View)
54-Pin TSOP
OPTIONS
MARKING
• Configurations
4 Meg x 16 (1 Meg x 16 x 4 banks)
4M16
•
Plastic Package – 54-pin TSOPII (400 mil)
- Alloy 42 lead frame - OCPL*
DG No. 901
- Copper lead frame
DGC
(Pb/Sn finish or RoHS available)
•
Note: “\” indicates an active low.
Timing (Cycle Time)
8ns; t
AC
= 6.5ns @ CL = 3 ( t
RP
- 24ns)
10ns; t
AC
= 9ns @ CL = 2
Operating Temperature Ranges
-Industrial Temp (-40°C to 85° C)
-Enhanced Temp
(-40°C to +105°C)
-Military Temp (-55°C to 125°C)
KEY TIMING PARAMETERS
SPEED
GRADE
-8
-10
-8
-10
CLOCK
ACCESS TIME
FREQUENCY
CL = 2** CL = 3**
125 MHz
–
6.5ns
100 MHz
–
7ns
83 MHz
9ns
–
66 MHz
9ns
–
-8
-10
•
IT
ET
XT
4 Meg x 16
Configuration
1 Meg x 16 x 4 banks
Refresh Count
4K
Row Addressing
4K (A0-A11)
Bank Addressing
4 (BA0, BA1)
Column Addressing
256 (A0-A7)
SETUP
TIME
2ns
3ns
2ns
3ns
HOLD
TIME
1ns
1ns
1ns
1ns
For more products and information
please visit our web site at
www.micross.com
*Off-center parting line
**CL = CAS (READ) latency
AS4SD4M16
Rev. 2.6 04/10
Micross Components reserves the right to change products or specifications without notice.
1
SDRAM
AS4SD4M16
GENERAL DESCRIPTION
The 64Mb SDRAM is a high-speed CMOS, dynamic ran-
dom-access memory containing 67,108,864 bits. It is internally
configured as a quad-bank DRAM with a synchronous interface
(all signals are registered on the positive edge of the clock signal,
CLK). Each of the x16’s 6,777,216-bit banks is organized as
4,096 rows by 256 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin
with the registration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address bits registered
coincident with the ACTIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-A11 select
the row). The address bits registered coincident with the READ or
WRITE command are used to select the starting column location
for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst
terminate option. An AUTO PRECHARGE function may be en-
abled to provide a self-timed row precharge that is initiated at the
end of the burst sequence.
The 64Mb SDRAM uses an internal pipelined architecture
to achieve high-speed operation. This architecture is compatible
with the 2n rule of prefetch architectures, but it also allows the
column address to be changed on every clock cycle to achieve a
high-speed, fully random access. Precharging one bank while ac-
cessing one of the other three banks will hide the precharge cycles
and provide seamless, high-speed, random-access operation.
The 64Mb SDRAM is designed to operate in 3.3V, low-power
memory systems. An auto refresh mode is provided, along with
a power-saving, power-down mode. All inputs and outputs are
LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating
performance, including the ability to synchronously burst data at a
high data rate with automatic column-address generation, the abil-
ity to interleave between internal banks in order to hide precharge
time and the capability to randomly change column addresses on
each clock cycle during a burst access.
AS4SD4M16
Rev. 2.6 04/10
Micross Components reserves the right to change products or specifications without notice.
2
SDRAM
AS4SD4M16
FUNCTIONAL BLOCK DIAGRAM
4 Meg x 16 SDRAM
CKE
CLK
CS\
WE\
CAS\
RAS\
CONTROL
LOGIC
COMMAND
DECODE
BANK1
BANK2 BANK3
MODE REGISTER
REFRESH
12
COUNTER
12
1
2
ROW
ADDRESS
MUX
12
12
BANK0
ROW-
ADDRESS
LATCH &
DECODER
4096
BANK 0
MEMORY
ARRAY
(4,096 X 256 X 16)
SENSE AMPLIFIERS
4096
2
2
DQML, DQMH
16
DATA
OUTPUT
REGISTER
16
DQ0-DQ15
2
A0,
A10,
BA
14
ADDRESS
REGISTER
2
BANK
CONTROL
LOGIC
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
256
(X16)
COLUMN
DECODER
16
DATA
INPUT
REGISTER
8
COLUMN-
ADDRESS
COUNTER/
LATCH
8
AS4SD4M16
Rev. 2.6 04/10
Micross Components reserves the right to change products or specifications without notice.
3
SDRAM
AS4SD4M16
ENHANCING RELIABILITY WITH COPPER LEAD FRAMES
1
ADVANTAGES & BENEFITS
•
Superior thermal conductivity improvement: 170 W/m*K
vs. 14 W/m*K (a 12X difference).
•
θ
ja and
θ
jc characteristics provide up to 3.8X advantage
of heat dissipation capability versus parts with alloy 42
lead frames.
• Heat dissipated from the die faster makes it run cooler
leading to longer life.
• Solder joint reliability vastly improved.
- CTE of Copper (17 ppm/
o
C), matches the CTE of Typical
FR4 PWBs (15-17 ppm/
o
C)
- CTE of Alloy 42 (5 ppm/
o
C), mismatch to CTE of FR4
PWBs (15-17 ppm/
o
C)
• RoHS Version (NiPdAu plating)
- Most preferred for elimination of risk for whisker growth.
The use of copper lead frames inherently allow for better solder joint reliability, tin whisker prevention and
better thermal dissipation. These are three big factors in overall system reliability over time.
Better Solder Joint Reliability
Many systems are expected to operate reliably over broad temperature variations spanning the industrial
(-40
0
C to +85
0
C) and military (-55
0
C to +125
0
C) temperature ranges. System problems can be caused
by the mismatch of thermal coefficients of all system components. Better solder joint reliability is obtained
since the copper lead frame is more
fl
exible, and the CTE of the copper lead frame is better matched with
that of typical FR4 PWBs, than that of Alloy 42. Repeated thermal cycles over a period of time can take a
toll on solder joints, causing cracks and intermittent connections where expansion and contraction of the
lead frame is at a different rate than the FR4 PWB that it is attached to.
Whisker Prevention
The RoHS version of this copper lead frame, with its’ NiPdAu (Nickel-Palladium-Gold) plating, eliminates
the risk of tin whiskers. Microscopic whiskers can grow on a parts’ pins than have tin content in the plat-
ing. Traditionally Alloy 42 lead frames have a Sn or PbSn plating. This plating containing tin, along with
certain environmental conditions can cause these whiskers to grow. Their growth may extend to form a
bridge with another pin on the device, or the whisker may break off and cause a short circuit or even an
explosive power surge on the board. The organization, iNEMI (International Electronics Manufacturing
Initiative) lists the NiPdAu lead plating as the most preferred for elimination of risk for whiskers.
Better Thermal Dissipation
Because copper has a 10X to 12X improvement in thermal conductivity vs. Alloy 42, and since
θ
ja and
θ
jc
characteristics of copper provide up to 3.8X advantage over Alloy 42, more efficient thermal dissipation is
the result. This translates to better heat dissipated away from the chip through the lead frame and PWB,
thus extending the useful life of the die by reducing die junction temperature. Therefore less heat stress
remains in the device, which is a leading cause of non-mechanical failure in a long life application.
1
Source: ISSI white paper; “Enhancing Long-Term Reliability with Copper Lead Frames.”
AS4SD4M16
Rev. 2.6 04/10
Micross Components reserves the right to change products or specifications without notice.
4
SDRAM
AS4SD4M16
ENHANCING RELIABILITY WITH COPPER LEAD FRAMES
Thermal Impedance Data - Cu LF vs. Alloy 42, 54 Lead TSOP II
Cu LF
ja
o
C/Watt
64M
128M
256M
512M
62
53
32.3
25.2
Cu LF
jc
o
C/Watt
9
7.8
2.7
2.8
Alloy 42 LF
ja
o
C/Watt
2 Layer
99.1
86.2
81
62.6
Alloy 42 LF
ja
o
C/Watt
4 Layer
70.5
58.9
44
39.2
Alloy 42 LF
jc
o
C/Watt
13.7
11.3
10.3
6.7
ja
Cu LF Advantage
1.6X
1.6X
2.5X
2.5X
jc
Cu LF Advantage
1.5X
1.4X
3.8X
2.4X
With copper lead frames, the die stays cooler, and results in greater component
reliability and longer life. This equates to improved system reliability and lower
service costs and greater system quality confidence.
AS4SD4M16
Rev. 2.6 04/10
Micross Components reserves the right to change products or specifications without notice.
5
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