DS89C430/DS89C440/DS89C450
Ultra-High-Speed Flash Microcontrollers
www.maxim-ic.com
GENERAL DESCRIPTION
The DS89C430, DS89C440, and DS89C450 offer the
highest performance available in 8051-compatible
microcontrollers. They feature newly designed
processor cores that execute instructions up to 12
times faster than the original 8051 at the same
crystal speed. Typical applications will experience a
speed improvement up to 10x. At 1 million
instructions per second (MIPS) per megahertz, the
microcontrollers achieve 33 MIPS performance from
a maximum 33MHz clock rate.
The
Ultra-High-Speed Flash Microcontroller User’s Guide
should
be used in conjunction with this data sheet.
Download it at
www.maxim-ic.com/microcontrollers.
§
FEATURES
High-Speed 8051 Architecture
One Clock-Per-Machine Cycle
DC to 33MHz Operation
Single Cycle Instruction in 30ns
Optional Variable Length MOVX to Access
Fast/Slow Peripherals
Dual Data Pointers with Automatic
Increment/Decrement and Toggle Select
Supports Four Paged Memory-Access Modes
On-Chip Memory
16kB/32kB/64kB Flash Memory
In-Application Programmable
In-System Programmable Through Serial Port
1kB SRAM for MOVX
80C52 Compatible
8051 Pin and Instruction Set Compatible
Four Bidirectional, 8-Bit I/O Ports
Three 16-Bit Timer Counters
256 Bytes Scratchpad RAM
Power-Management Mode
Programmable Clock Divider
Automatic Hardware and Software Exit
ROMSIZE Feature
Selects Internal Program Memory Size from
0 to 64kB
Allows Access to Entire External Memory Map
Dynamically Adjustable by Software
Peripheral Features
Two Full-Duplex Serial Ports
Programmable Watchdog Timer
13 Interrupt Sources (Six External)
Five Levels of Interrupt Priority
Power-Fail Reset
Early Warning Power-Fail Interrupt
Electromagnetic Interference (EMI) Reduction
§
ORDERING INFORMATION
PART
DS89C430-MNL
DS89C430-MNL+
DS89C430-QNL
DS89C430-QNL+
DS89C430-ENL
DS89C430-ENL+
DS89C440-MNL
DS89C440-MNL+
DS89C440-QNL
DS89C440-QNL+
DS89C440-ENL
DS89C440-ENL
DS89C450-MNL
DS89C450-MNL+
DS89C450-QNL
DS89C450-QNL+
DS89C450-ENL
DS89C450-ENL+
FLASH
MEMORY SIZE
16kB
16kB
16kB
16kB
16kB
16kB
32kB
32kB
32kB
32kB
32kB
32kB
64kB
64kB
64kB
64kB
64kB
64kB
PIN-PACKAGE
40 PDIP
40 PDIP
44 PLCC
44 PLCC
44 TQFP
44 TQFP
40 PDIP
40 PDIP
44 PLCC
44 PLCC
44 TQFP
44 TQFP
40 PDIP
40 PDIP
44 PLCC
44 PLCC
44 TQFP
44 TQFP
§
§
§
§
+
Denotes a lead-free/RoHS-compliant device.
Complete Selector Guide appears at end of data sheet.
Pin Configurations appear at end of data sheet.
APPLICATIONS
Data Logging
White Goods
Motor Control
Magstripe
Reader/Scanner
Telephones
HVAC
Vending
Gaming
Equipment
Building Energy
Control and
Management
Programmable
Logic Controllers
Uninterruptible
Power Supplies
Building Security
and Door Access
Control
Automotive Text
Equipment
Consumer
Electronics
Industrial Control
and Automation
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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REV: 060805
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground………………………………………………………………………-0.3V to (V
CC
+ 0.5V)
Voltage Range on V
CC
Relative to Ground…………………………………………………………………………………..-0.3V to +6.0V
Ambient Temperature Range (under bias)…………………………………………………………………………………-40°C to +85°C
Storage Temperature Range……………………………………………………………………………………………….-55°C to +125°C
Soldering Temperature…………………………………………………………………………………………See IPC/JEDEC J-STD-020
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 4.5V to 5.5V, T
O
= -40°C to +85°C.) (Note 1)
PARAMETER
Supply Voltage (Notes 2, 3)
Power-Fail Warning (Notes 2, 4)
Reset Trip Point (Min Operating Voltage) (Notes 2, 3, 4)
Supply Current, Active Mode (Note 5)
Supply Current, Idle Mode at 33MHz (Note 6)
Supply Current, Stop Mode, Bandgap Disabled (Note 7)
Supply Current, Stop Mode, Bandgap Enabled (Note 7)
Input Low Level (Note 2)
Input High Level (Note 2)
Input High Level XTAL and RST (Note 2)
Output Low Voltage, Port 1 and 3 at I
OL
= 1.6mA (Note 2)
Output Low Voltage, Port 0 and 2, ALE,
PSEN
at I
OL
= 3.2mA
(Note 2)
Output High Voltage, Port 1, 2, and 3, at I
OH
= -50mA
(Notes 2, 8)
Output High Voltage, Port 1, 2, and 3 at I
OH
= -1.5mA (Notes 2, 9)
Output High Voltage, Port 0, 1, 2, ALE,
PSEN, RD, WR
in Bus
Mode at I
OH
= -8mA (Notes 2, 10)
Output High Voltage, RST at I
OL
= -0.4mA (Note 2, 11)
Input Low Current, Port 1, 2, and 3 at 0.4V
Transition Current from 1 to 0, Port 1, 2, and 3 at 2V (Note 12)
Input Leakage Current, Port 0 in I/O Mode and
EA
(Note 13)
Input Current, Port 0 in Bus Mode (Note 14)
RST Pulldown Resistance (Note 13)
SYMBOL
V
CC
V
PFW
V
RST
I
CC
I
IDLE
I
STOP
I
SPBG
V
IL
V
IH
V
IH2
V
OL1
V
OL2
V
OH1
V
OH2
V
OH3
V
OH4
I
IL
I
TL
I
L
I
L
R
RST
2.4
2.4
2.4
2.4
-50
-650
-10
-300
50
120
+10
+300
200
-0.3
2.0
3.5
0.15
0.15
MIN
4.5
4.2
3.95
TYP
5.0
4.375
4.125
75
40
1
150
MAX
5.5
4.6
4.35
110
50
100
300
+0.8
V
CC
+ 0.3
V
CC
+ 0.3
0.45
0.45
UNITS
V
V
V
mA
mA
mA
mA
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
kW
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DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
Note 1:
Note 2:
Note 3:
Specifications to -40°C are guaranteed by design and not production tested.
All voltages are referenced to ground.
The user should note that this part is tested and guaranteed to operate down to 4.5V (10%) and that V
RST
(min) is specified below
that point. This indicates that there is a range of voltages [(V
MIN
to V
RST
(min)] where the processor's operation is not guaranteed, but
the reset trip point has not been reached. This should not be an issue in most applications, but should be considered when proper
operation must be maintained at all times. For these applications, it may be desirable to use a more accurate external reset.
While the specifications for V
PFW
and V
RST
overlap, the design of the hardware makes it so this is not possible. Within the ranges
given, there is guaranteed separation between these two voltages.
Active current is measured with a 33MHz clock source driving XTAL1, V
CC
= RST = 5.5V. All other pins are disconnected.
Idle mode current is measured with a 33MHz clock source driving XTAL1, V
CC
= 5.5V, RST at ground. All other pins are
disconnected.
Stop mode is measured with XTAL and RST grounded, V
CC
= 5.5V. All other pins are disconnected.
RST = 5.5V. This condition mimics the operation of pins in I/O mode.
During a 0-to-1 transition, a one shot drives the ports hard for two clock cycles. This measurement reflects a port pin in transition
mode.
When addressing external memory.
Guaranteed by design.
Ports 1, 2, and 3 source transition current when pulled down externally. The current reaches its maximum at approximately 2V.
RST = 5.5V. Port 0 is floating during reset and when in the logic-high state during I/O mode.
This port is a weak address holding latch in bus mode. Peak current occurs near the input transition point of the holding latch at
approximately 2V.
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
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DS89C430/DS89C440/DS89C450
AC CHARACTERISTICS
(V
CC
= 4.5V to 5.5V, T
O
= -40°C to +85°C.) (See
Figure 1, Figure 2,
and
Figure 3.)
1-CYCLE
PAGE MODE 1
MIN
System Clock External
Oscillator (Note 15)
System Clock External Crystal
(Note 15)
ALE Pulse Width (Note 16)
Port 0 Instruction Address Valid
to ALE Low
Port 2 Instruction Address Valid
to ALE Low
Port 0 Data AddressValid to
ALE Low
Program Address Hold After
ALE Low
Address Hold after ALE Low
MOVX Write
Address Hold after ALE Low
MOVX Read
ALE Low to Valid Instruction In
1/t
CLCL
1/t
CLCL
0
1
0.5t
CLCL
- 2
+ t
STC3
MAX
33
33
2-CYCLE
PAGE MODE 1
MIN
0
1
t
CLCL
- 2
+ t
STC3
MAX
33
33
4-CYCLE
PAGE MODE 1
MIN
0
1
2t
CLCL
- 4
+ t
STC3
MAX
33
33
PAGE MODE 2
MIN
0
1
1.5t
CLCL
- 5
+ t
STC3
t
CLCL
- 3
MAX
33
33
NONPAGE MODE
MIN
0
1
1.5t
CLCL
- 5
+ t
STC3
0.5t
CLCL
- 3
MAX
33
MHz
33
ns
PARAMETER
SYMBOL
UNITS
t
LHLL
t
AVLL
ns
t
AVLL2
0.5t
CLCL
- 4
0.5t
CLCL
- 4
1.5t
CLCL
- 4
0.5t
CLCL
- 4
t
CLCL
- 3 +
t
STC3
t
CLCL
- 4
0.5t
CLCL
- 3
+ t
STC3
1t
CLCL
- 10
0.5t
CLCL
- 8
+ t
STC2
0.5t
CLCL
- 8
+ t
STC2
2t
CLCL
- 6
2t
CLCL
- 6
ns
t
AVLL3
ns
t
LLAX
0.5t
CLCL
- 8
0.5t
CLCL
- 8
+ t
STC4
0.5t
CLCL
- 8
+ t
STC4
1.5t
CLCL
- 8
1.5t
CLCL
- 8
+ t
STC4
1.5t
CLCL
- 8
+ t
STC4
2.5t
CLCL
- 8
2.5t
CLCL
- 8
+ t
STC3
2.5t
CLCL
- 8
+ t
STC3
1t
CLCL
- 10
0.5t
CLCL
- 8
+ t
STC2
0.5t
CLCL
- 8
+ t
STC3
ns
t
LLAX2
ns
t
LLAX3
ns
t
LLIV
ns
ALE Low to
PSEN
Low
PSEN
Pulse Width for Program
Fetch
t
LLPL
1.5t
CLCL
- 6
0.5t
CLCL
- 2
ns
t
PLPH
t
CLCL
- 5
t
CLCL
- 5
2t
CLCL
- 5
t
CLCL
- 5
2t
CLCL
- 5
ns
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DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
AC CHARACTERISTICS (continued)
(V
CC
= 4.5V to 5.5V, T
O
= -40°C to +85°C.) (See
Figure 1, Figure 2,
and
Figure 3.)
PARAMETER
SYMBOL
1-CYCLE
PAGE MODE 1
MIN
PSEN
Low to Valid Instruction
In
Input Instruction Hold After
PSEN
Input Instruction Float After
PSEN
Port 0 Address to Valid
Instruction In
Port 2 Address to Valid
Instruction In
PSEN
Low to Port 0 Address
Float
RD
Pulse Width (P3.7)
(Note 16)
WR
Pulse Width (P3.6)
(Note 16)
RD
(P3.7) Low to Valid Data In
(Note 16)
Data Hold After
RD
(P3.7)
t
PLIV
MAX
t
CLCL
- 20
2-CYCLE
PAGE MODE 1
MIN
MAX
t
CLCL
- 20
4-CYCLE
PAGE MODE 1
MIN
MAX
2t
CLCL
- 20
PAGE MODE 2
MIN
MAX
t
CLCL
- 20
NONPAGE MODE
MIN
MAX
2t
CLCL
- 20
ns
UNITS
t
PXIX
0
0
0
0
0
ns
t
PXIZ
t
CLCL
- 5
t
CLCL
- 5
ns
t
AVIV0
1.5t
CLCL
- 22
3t
CLCL
- 22
ns
t
AVIV2
t
CLCL
- 20
1.5t
CLCL
- 20
2.5t
CLCL
- 20
3t
CLCL
- 20
3.5t
CLCL
- 20
ns
t
PLAZ
t
CLCL
- 5
+ t
STC1
t
CLCL
- 5
+ t
STC1
t
CLCL
- 18
+ t
STC1
0
0
t
CLCL
- 5
+ t
STC1
t
CLCL
- 5
+ t
STC1
t
CLCL
- 18
+ t
STC1
0
2t
CLCL
- 5
+ t
STC1
2t
CLCL
- 5
+ t
STC1
2t
CLCL
- 18
+ t
STC1
0
2t
CLCL
- 5
+ t
STC1
2t
CLCL
- 5
+ t
STC1
0
2t
CLCL
- 5
+ t
STC1
2t
CLCL
- 5
+ t
STC1
2t
CLCL
- 18
+ t
STC1
0
0
ns
t
RLRH
ns
t
WLWH
ns
t
RLDV
2t
CLCL
- 18
+ t
STC1
ns
t
RHDX
ns
Data Float After
RD
(P3.7)
MOVX ALE Low to Input Data
Valid (Note 16)
t
RHDZ
t
CLCL
- 5
2t
CLCL
- 8
+ t
STC1
t
CLCL
- 5
2t
CLCL
- 5
+ t
STC1
ns
t
LLDV
ns
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