200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 1Gb 1st ver.
This Hynix unbuffered Slim Outline Dual In-Line Memory Module(DIMM) series consists of 1Gb 1st ver. DDR2 SDRAMs
in Fine Ball Grid Array(FBGA) packages on a 200pin glass-epoxy substrate. This Hynix 1Gb 1st ver. based Unbuffered
DDR2 SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of industry standard.
It is suitable for easy interchange and addition.
FEATURES
•
JEDEC standard Double Data Rate2 Synchronous
DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power
Supply
•
All inputs and outputs are compatible with SSTL_1.8
interface
•
•
•
Posted CAS
Programmable CAS Latency 3 ,4 ,5
OCD (Off-Chip Driver Impedance Adjustment) and
ODT (On-Die Termination)
•
•
Fully differential clock operations (CK & CK)
Programmable Burst Length 4 / 8 with both
sequential and interleave mode
•
•
•
•
•
•
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
Serial presence detect with EEPROM
DDR2 SDRAM Package: 68 ball FBGA
67.60 x 30.00 mm form factor
Lead-free Products are RoHS compliant
ORDERING INFORMATION
Part Name
HYMP112S648-E3/C4/Y5
HYMP325S64M*8-E3/C4/Y5
HYMP112S64P8-E3/C4/Y5
HYMP325S64M*P8-E3/C4/Y5
Notes:
* : ‘M’ stands for Hynix Dual Die Package(DDP) based module.
Density
1GB
2GB
1GB
2GB
Organization
128Mx64
256Mx64
128Mx64
256Mx64
# of
DRAMs
8
16
8
16
# of
ranks
1
2
1
2
Materials
Leaded
Leaded
Lead free
Lead free
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.2 / Sep. 2005
1
1200pin
Unbuffered DDR2 SDRAM SO-DIMMs
PIN DESCRIPTION
Symbol
Type
Polarity
Cross
Point
Pin Description
The system clock inputs. All adress an commands lines are sampled on the cross point
CK[1:0], CK[1:0]
Input
of the rising edge of CK and falling edge of CK. A Delay Locked Loop(DLL) circuit is
driven from the clock inputs and output timing for read operations is synchronized to
the input clock.
CKE[1:0]
Input
Active
High
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when
low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self
Refresh mode.
Enables the associated DDR2 SDRAM command decoder when low and disables the
S[1:0]
Input
Active
Low
Active
Low
command decoder when high. When the command decoder is disabled, new commands
are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is
selected by S1
RAS, CAS, WE
BA[2:0]
ODT[1:0]
Input
Input
Input
Active
High
When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS,
RAS and WE define the operation to be excecuted by the SDRAM.
Selects which DDR2 SDRAM internal bank of four or eight is activated.
Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2
SDRAM mode register.
During a Bank Activate command cycle, difines the row address when sampled at the
cross point of the rising edge of CK and falling edge of CK. During a Read or Write com-
mand cycle, defines the column address when sampled at the cross point of the rising
edge of CK and falling edge of CK. In addition to the column address, AP is used to
A[9:0], A10/AP,
A[15:11]
Input
invoke autoprecharge operation at the end of the burst read or write cycle. If AP is
high., autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP
is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in
conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks
will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn
are used to define which bank to precharge.
DQ[63:0]
DM[7:0]
In/Out
Input
Active
High
Data Input/Output pins.
The data write masks, associated with one data byte. In Write mode, DM operates as a
byte mask by allowing input data to be written if it is low but blocks the write operation
if it is high. In Read mode, DM lines have no effect.
The data strobe, associated with one data byte, sourced whit data transfers. In Write
mode, the data strobe is sourced by the controller and is centered in the data window.
DQS[7:0], DQS[7:0] In/Out
Cross
point
In Read mode, the data strobe is sourced by the DDR2 SDRAMs and is sent at leading
edge of the data window. DQS signals are complements, and timing is relative to the
crosspoint of respective DQS and DQS. If the module is to be operated in single ended
strobe mode, all DQS signals must be tied on the system board to VSS and DDR2
SDRAM mode registers programmed approriately.
V
DD
, V
DD
SPD,V
SS
SDA
SCL
SA[1:0]
TEST
Supply
In/Out
Input
Input
In/Out
Power supplies for core, I/O, Serial Presense Detect, and ground for the module.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A
resister must be connected to V
DD t
o act as a pull up.
This signals is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from SCL to VDD to act as a pull up.
Address pins used to select the Serial Presence Detect base address.
The TEST pin is reserved for bus analysis tools and is not connected on normal memory
modules(SODIMMs).
Rev. 1.2 / Sep. 2005
3
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