CXA2027Q
Analog signal processor IC
Description
The CXA2027Q is an analog signal processor for
CCD linear image sensor output signal. This device
is suitable for 3 lines of full-color CCD linear image
sensor (ILX516K/ILX518K/ILX520K: 3648 pixels
×
3 lines/5363 pixels
×
3 lines/7078 pixels
×
3 lines).
This device has a built-in sample-and-hold, clamp,
multiplex, gain control amplifier circuits and can be
connected directly with external AD converters.
(Sony’s CXD2311AR, CXD1175AM or CXA1977R
are recommended as AD converters.)
Features
•
Sample-and-hold circuit
•
Pixel-clamp and line-clamp circuit
•
•
•
•
•
Multiplex circuit
ADC driver circuit
Gain control amplifier circuit
Offset control circuit
Clock frequency: 1.5 to 6MHz (after multiplex)
48 pin QFP (Plastic)
Absolute Maximum Ratings
•
Supply voltage
•
Input voltage
•
Output voltage
–0.3 to 7
V
CC
V
I
–0.3 to V
CC
+ 0.3
V
O
–0.3 to V
CC
+ 0.3
–55 to +150
640
V
V
V
°C
mW
•
Storage temperature Tstg
•
Allowable power dissipation
P
D
Applications
Color image scanner
Structure
Bipolar silicon monolithic IC
Operating Conditions
(Typ. in parentheses)
•
Supply voltage
V
CC
4.75 to 5.25 (5.0) V
•
Digital input voltage High V
IH
3.5 to V
CC
(V
CC
) V
•
Digital input voltage Low V
IL
0 to 0.8 (0)
V
•
Operating temperature Topr
0 to +70
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95210A78
CXA2027Q
Block Diagram and Pin Configuration
MPX2
G-IN
BUF
MPX1
R-IN
TD3
TD1
CLP
TD2
TD5
26
36
B-IN
37
35
34
33
32
31
30
29
28
27
25
24 TD4
23 LCLP
LPR 38
GCA
LPG
LPB
D4-0
VCCA
D4-1
39
40
41
42
43
S/H
S/H
GCA
TD6
22 GC
21 VCCP
20 SIGOUT
19
GND
18 VRT
17
VRB
16 CLPC
15
LD4
14 LD3
13
LD2
12
SH
S/H
GCA
DC shift
Driver
V
REF
D4-2 44
D4-3 45
D4-4
46
D/A
GCA
LOG
D/A
LATCH
LOG
D/A
LATCH
LOG
D/A
LATCH
VCCD 47
D5-0 48
D/A
D/A
1
2
3
4
5
6
7
8
9
10
11
D5-1
D6-1
D6-4
D5-4
D6-2
D5-2
D6-0
D6-3
D6-5
D5-3
–2–
LD0
LD1
CXA2027Q
Pin Description
Pin Symbol
(I/O)
No.
Typical pin voltage
Equivalent circuit
DC
AC
5-bit data input pin 1 for
G channel pixel clamp
voltage adjustment (LSB)
5-bit data input pin 2 for
G channel pixel clamp
voltage adjustment
5-bit data input pin 3 for
G channel pixel clamp
voltage adjustment
5-bit data input pin 4 for
G channel pixel clamp
voltage adjustment
5-bit data input pin 5 for
G channel pixel clamp
voltage adjustment (MSB)
5-bit data input pin 1 for
B channel pixel clamp
voltage adjustment (LSB)
5-bit data input pin 2 for
B channel pixel clamp
voltage adjustment
5-bit data input pin 3 for
B channel pixel clamp
voltage adjustment
5-bit data input pin 4 for
B channel pixel clamp
voltage adjustment
5-bit data input pin 5 for
B channel pixel clamp
voltage adjustment (MSB)
6-bit data input pin 1 for
SIGOUT output line clamp
voltage adjustment (LSB)
6-bit data input pin 2 for
SIGOUT output line clamp
voltage adjustment
1.8V
Description
48
D5-0 (I)
1
D5-1 (I)
2
D5-2 (I)
3
D5-3 (I)
VCCD
VCCD
4
D5-4 (I)
Lo: 0 to 0.8V
Hi: 3.5 to 5V
48
129
1.5k
1.8V
41
D4-0 (I)
100µ
43
D4-1 (I)
44
D4-2 (I)
45
D4-3 (I)
46
D4-4 (I)
5
D6-0 (I)
6
D6-1 (I)
VCCD
VCCD
7
D6-2 (I)
Lo: 0 to 0.8V
Hi: 3.5 to 5V
5
129
1k
6-bit data input pin 3 for
SIGOUT output line clamp
voltage adjustment
6-bit data input pin 4 for
SIGOUT output line clamp
voltage adjustment
6-bit data input pin 5 for
SIGOUT output line clamp
voltage adjustment
6-bit data input pin 6 for
SIGOUT output line clamp
voltage adjustment (MSB)
8
D6-3 (I)
100µ
9
D6-4 (I)
10
D6-5 (I)
–3–
CXA2027Q
Pin Symbol
(I/O)
No.
11
LD0 (I)
Typical pin voltage
Equivalent circuit
DC
AC
5-bit data input pin 1 for
pre-stage GCA gain
adjustment (LSB)
VCCD
VCCD
Description
12
LD1 (I)
Lo:
0 to 0.8V
Hi:
3.5 to 5V
20k
11
129
1.5k
5-bit data input pin 2 for
pre-stage GCA gain
adjustment
5-bit data input pin 3 for
pre-stage GCA gain
adjustment
5-bit data input pin 4 for
pre-stage GCA gain
adjustment
5-bit data input pin 5 for
pre-stage GCA gain
adjustment (MSB)
13
LD2 (I)
14
LD3 (I)
15
LD4 (I)
VCCA
VCCA
1.5k
16
CLPC
Approx.
3.1V
16
129
Additional capacitance pin
for line clamp.
Add 0.47µF between this
pin and GND.
6.7µ
VCCA
6k
17
VCCA
2.0V
3k
2k
VCCA
VCCA
100µ
100µ
17
VRB (O) 2.0V
Output pin for AD converter
reference voltage VRB
100µ
1k
75µ
VCCA
VCCA
187.5
VCCA
2k
18
VRT (O) 4.0V
18
750
Output pin for AD converter
reference voltage VRT
4k
100µ
19
GND
0V
–4–
GND pin
CXA2027Q
Pin Symbol
(I/O)
No.
Typical pin voltage
Equivalent circuit
DC
AC
VCCA
VCCA
21
100µ
1k
20
2mA
Description
20
SIGOUT
(O)
2.0V
+MAX1.8V
(2.0 to 3.8V)
Signal output pin
(to AD converter)
21
VCCP
5V
VCCA
VCCA
20k
VCCA
100µ
Power supply pin
(for signal output system)
22
GC (I)
0 to 5V
129
22
4k
30k
1.5k
Voltage input pin for post-
stage GCA gain adjustment
(Can be open; in that case
outputs 3V)
Lo: 0 to 0.8V
Hi: 3.5 to 5V
23
LCLP (I)
VCCA
VCCA
100µ
Lo:
clamp OFF
Hi:
clamp ON
1.5V
23
129
2k
Line clamp pulse input pin
(Apply high level during the
optical black period of CCD
output)
24
25
26
27
28
29
TD4 (O) 1.7 to 3.6V
TD6 (O) 2.0 to 3.6V
TD5 (O)
TD1 (O)
TD2 (O)
TD3 (O)
Lo: 0 to 0.8V
Hi: 3.5 to 5V
1.7 to 3.6V
24
VCCA
VCCA
DA4 analog output test pin
DA6 analog output test pin
DA5 analog output test pin
(Use with open)
129
126µ
DA1 analog output test pin
DA2 analog output test pin
DA3 analog output test pin
VCCA
VCCA
250µ
30
CLP (I)
129
Lo:
clamp OFF
Hi:
clamp ON
1.5V
1k
30
Pixel clamp pulse input pin
(Apply high level during the
precharge period of CCD
output)
VCCA
VCCA
1.5k
31
MPX1 (I)
Lo: 0 to 0.8V
Hi: 3.5 to 5V
1.2V
31
129
100µ
MPX channel switching
pulse input pin 1
(See high/low table under
Pin 32 in following section.)
–5–
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