ADVANCE
TECHNOLOGY, INC.
MT4LDT164H(X)(L), MT8LDT264H(X)(L)
1 MEG, 2 MEG x 64 DRAM MODULES
SMALL-OUTLINE
DRAM MODULE
FEATURES
• JEDEC- and industry-standard pinout in a 144-pin,
small-outline, dual-in-line memory module (DIMM)
• High-performance CMOS silicon-gate process
• Single +3.3V
±0.3V
power supply
• All device pins are TTL-compatible
• Low power, 24mW standby; 1,012mW active, typical
(16MB)
• Refresh modes: RAS# ONLY, CAS#-BEFORE-RAS#
(CBR) and HIDDEN; optional Extended CBR
• 1,024-cycle refresh distributed across 16ms or
1,024-cycle extended refresh distributed across 128ms
• FAST PAGE MODE (FPM) operating mode or
Extended Data-Out (EDO) PAGE MODE operating
mode
• Serial Presence-Detect (SPD)
1 MEG, 2 MEG x 64
8, 16 MEGABYTE, 3.3V, OPTIONAL
EXTENDED REFRESH, FAST PAGE OR EDO
PAGE MODE
PIN ASSIGNMENT (Front View)
144-Pin Small-Outline DIMM
OPTIONS
• Timing
60ns access
70ns access
• Packages
144-pin Small-Outline DIMM (gold)
• Operating Modes
FAST PAGE MODE
EDO PAGE MODE
• Refresh
Standard/16ms
Extended Refresh/128ms
MARKING
-6
-7
G
Blank
X
Blank
L
KEY TIMING PARAMETERS
EDO Operating Mode
SPEED
-6
-7
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
105ns
125ns
60ns
70ns
25ns
30ns
30ns
35ns
15ns
20ns
12ns
12ns
FPM Operating Mode
SPEED
-6
-7
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
RP
110ns
130ns
60ns
70ns
35ns
40ns
30ns
35ns
15ns
20ns
40ns
50ns
PIN #
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
FRONT
V
SS
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
V
SS
CAS0#
CAS1#
Vcc
A0
A1
A2
V
SS
DQ8
DQ9
DQ10
DQ11
V
CC
DQ12
DQ13
DQ14
DQ15
V
SS
RSVD
RSVD
RFU
Vcc
RFU
WE#
RAS0#
RAS1#*
PIN #
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
BACK
V
SS
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
V
SS
CAS4#
CAS5#
Vcc
A3
A4
A5
V
SS
DQ40
DQ41
DQ42
DQ43
V
CC
DQ44
DQ45
DQ46
DQ47
V
SS
RSVD
RSVD
RFU
Vcc
RFU
RFU
RFU
RFU
PIN #
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
FRONT
OE#
V
SS
RSVD
RSVD
Vcc
DQ16
DQ17
DQ18
DQ19
V
SS
DQ20
DQ21
DQ22
DQ23
Vcc
A6
A8
V
SS
A9
A10
V
CC
CAS2#
CAS3#
V
SS
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
V
SS
SDA
Vcc
PIN #
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
BACK
RFU
V
SS
RSVD
RSVD
Vcc
DQ48
DQ49
DQ50
DQ51
V
SS
DQ52
DQ53
DQ54
DQ55
Vcc
A7
RSVD
V
SS
RSVD
RSVD
V
CC
CAS6#
CAS7#
V
SS
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
V
SS
SCL
Vcc
*16MB version only
MT4LDT164H(X)(L), MT8LDT264H(X)(L)
DM66.pm5 – Rev. 3/96
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1996,
Micron Technology, Inc.
ADVANCE
TECHNOLOGY, INC.
MT4LDT164H(X)(L), MT8LDT264H(X)(L)
1 MEG, 2 MEG x 64 DRAM MODULES
cycles. Returning RAS# HIGH terminates the FAST PAGE
MODE operation.
PART NUMBERS
EDO Operating Mode
PART NUMBER
MT4LDT164HG-xx X
MT4LDT164HG-xx XL
MT8LDT264HG-xx X
MT8LDT264HG-xx XL
xx = speed
DESCRIPTION
1 Meg x 64, EDO
1 Meg x 64, EDO, Extended Refresh
2 Meg x 64, EDO
2 Meg x 64, EDO, Extended Refresh
EDO PAGE MODE
EDO PAGE MODE, designated by the “X” option, is an
accelerated FAST PAGE MODE cycle. The primary advan-
tage of EDO is the availability of data-out even after CAS#
goes back HIGH. EDO provides for CAS# precharge time
(
t
CP) to occur without the output data going invalid. This
elimination of CAS# output control provides for pipeline
READs.
FAST PAGE MODE modules have traditionally turned
the output buffers off (High-Z) with the rising edge of
CAS#. EDO operates as any DRAM READ or FAST-PAGE-
MODE READ, except data will be held valid after CAS#
goes HIGH, as long as RAS# and OE# are held LOW and
WE# is held HIGH (reference MT4LC1M16E5 DRAM data
sheet for additional information on EDO functionality).
FPM Operating Mode
PART NUMBER
MT4LDT164HG-xx
MT4LDT164HG-xx L
MT8LDT264HG-xx
MT8LDT264HG-xx L
xx = speed
DESCRIPTION
1 Meg x 64
1 Meg x 64, Extended Refresh
2 Meg x 64
2 Meg x 64, Extended Refresh
GENERAL DESCRIPTION
The MT4LDT164H(X)(L) and MT8LDT264H(X)(L) are
randomly accessed 8MB and 16MB solid-state memories
organized in a small outline x64 configuration. They are
specially processed to operate from +3.0V to 3.6V for low
voltage memory systems.
During READ or WRITE cycles, each bit is uniquely
addressed through the 20 address bits which are entered 10
bits (A0 -A9) at a time. RAS# is used to latch the first 10 bits
and CAS# the latter 10 bits.
READ and WRITE cycles are selected with the WE#
input. A logic HIGH on WE# dictates READ mode, while a
logic LOW on WE# dictates WRITE mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE# or
CAS#, whichever occurs last. If WE# goes LOW prior to
CAS# going LOW, the output pin(s) remain open (High-Z)
until the next CAS# cycle.
REFRESH
Memory cell data is retained in its correct state by main-
taining power and executing any RAS# cycle (READ,
WRITE) or RAS# refresh cycle (RAS# ONLY, CBR or HID-
DEN) so that all combinations of RAS# addresses (A0 -A9)
are executed at least every
t
REF, regardless of sequence.
The CBR REFRESH cycle will invoke the internal refresh
counter for automatic RAS# addressing.
STANDBY
Returning RAS# and CAS# HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during
the RAS# HIGH time.
SERIAL PRESENCE-DETECT EEPROM
This module incorporates Serial Presence Detect (SPD).
The SPD function is implemented using a 2,048 bit EEPROM.
This nonvolatile storage device contains data programmed
by Micron that identifies the module type and various
DRAM organization and timing parameters. System READ/
WRITE operations to the EEPROM device occur via a
standard I
2
C bus using the DIMM’s SCL (clock) and SDA
(data) signals. The EEPROM device operates with a Vcc of
3.3V
±0.3V.
FAST PAGE MODE
FAST PAGE MODE operations allow faster data opera-
tions (READ or WRITE) within a row-address-defined
(A0 -A9) page boundary. The FAST PAGE MODE cycle is
always initiated with a row-address strobed-in by RAS#,
followed by a column-address strobed-in by CAS#. CAS#
may be toggled-in by holding RAS# LOW and strobing-in
different column-addresses, thus executing faster memory
MT4LDT164H(X)(L), MT8LDT264H(X)(L)
DM66.pm5 – Rev. 3/96
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1996,
Micron Technology, Inc.
ADVANCE
TECHNOLOGY, INC.
MT4LDT164H(X)(L), MT8LDT264H(X)(L)
1 MEG, 2 MEG x 64 DRAM MODULES
SERIAL PRESENCE-DETECT EEPROM
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1) (V
CC
= +3.3V
±0.3V)
PARAMETER/CONDITION
Supply Voltage
Input High (Logic 1) Voltage, all inputs
Input Low (Logic 0) Voltage, all inputs
OUTPUT LOW VOLTAGE, I
OUT
= 3mA
INPUT LEAKAGE CURRENT, V
IN
= GND to V
CC
OUTPUT LEAKAGE CURRENT, V
OUT
= GND to V
CC
STANDBY CURRENT
SCL = SDA = V
CC
-0.3V, All other inputs = GND or V
CC
3.3V +10%
POWER SUPPLY CURRENT
SCL clock frequency = 100 KHz
SYMBOL
V
CC
V
IH
V
IL
V
OL
I
LI
I
LO
I
SB
I
CC
MIN
3.0
-1.0
MAX
3.6
V
CC
×
.3
0.4
10
10
30
2
UNITS
V
V
V
V
µA
µA
µA
mA
NOTES
V
CC
×
.7 V
CC
×
.5
SERIAL PRESENCE-DETECT EEPROM
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 1) (V
CC
= +3.3V
±0.3V)
AC CHARACTERISTICS
PARAMETER/CONDITION
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
SYMBOL
t
AA
t
BUF
t
DH
t
F
t
HD:DAT
t
HD:STA
t
HIGH
t
I
t
LOW
t
R
t
SCL
t
SU:DAT
t
SU:STA
t
SU:STO
t
WR
MIN
0.3
4.7
300
0
4
4
MAX
3.5
300
100
4.7
1
100
250
4.7
4.7
10
UNITS
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
KHz
ns
µs
µs
ms
NOTES
32
MT4LDT164H(X)(L), MT8LDT264H(X)(L)
DM66.pm5 – Rev. 3/96
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1996,
Micron Technology, Inc.
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