HCPL-0872
Digital Interface IC
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
The Digital Interface IC, HCPL-0872 converts the single-
bit data stream from the Isolated Modulator (such as
HCPL-7860/786J/7560) into fifteen-bit output words and
provides a serial output interface that is compatible with
SPI
®
, QSPI
®
, and Microwire
®
protocols, allowing direct
connection to a microcontroller. The Digital Interface IC,
HCPL-0872 is available in a 300-mil wide SO-16 surface-
mount package. Features of the Digital Interface IC
include five different conversion modes, three different
pre-trigger modes, offset calibration, fast over-range
detection, and adjustable threshold detection. Program-
mable features are configured via the Serial Configura-
tion port. A second multiplexed input is available to allow
measurements with a second isolated modulator without
additional hardware.
Features
•
Interface between HCPL-7860/786J/7560 and MCU/
DSP
•
5 Conversion Modes for Resolution/Speed Trade-Off
•
3 Pre-Trigger Modes
•
Offset Calibration
•
Fast 3 µs Over-Range Detection
•
Adjustable Threshold Detection
•
Serial I/O (SPI
®
, QSPI
®
and Microwire Compatible)
•
Offset Calibration
•
-40°C to +85°C Operating Temperature Range
Applications
•
Motor Phase and Rail Current Sensing
•
Data Acquisition Systems
•
Industrial Process Control
•
Inverter Current Sensing
•
General Purpose Current Sensing and Monitoring
V
DD1
Input
Current
V
DD2
MCLK
MDAT
GND2
1
2
3
4
5
6
7
8
CCLK
V
IN+
V
IN-
-
GND1
CONFIG
-
CLAT
INTER-
CHAN
FACE CON
VERSION
CDAT
SCLK
INTER-
-
FACE
V
DD
16
15
14
13
12
11
10
9
MCLK1
MDAT1
MCLK2
SDAT
HCPL-7860
HCPL-786J
HCPL-7560
V
DD1
Input
Current
CH1
CS
THR1
MCU
or
DSP
V
DD2
MCLK
MDAT
GND2
V
IN+
V
IN-
-
GND1
THRES
MDAT2
CH2 HOLD
OVR1
DETECT
& RESET
GND
RESET
HCPL-0872
A 0.1 µF bypass capacitor must be connected between pins V
DD
and Ground
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation, which may be induced by ESD.
SPI and QSPI are trademarks of Motorola Corp.
Microwire is a trademark of National Semiconductor Inc.
HCPL-0872 Digital Interface IC
Because the two inputs are multiplexed, only one con-
version at a time can be made and not all features are
available for the second channel. The available features
for both channels are shown in the table below
Feature
Conversion Mode
Offset Calibration
Pre-Trigger Mode
Over-Range Detection
Adjustable Threshold
Detection
Channel 1
•
•
•
•
•
Channel 2
•
•
CCLK 1
CLAT 2
CDAT 3
MCLK1 4
MDAT1 5
MCLK2 6
MDAT2 7
GND 8
CH2
CONFIG.
INTER-
FACE
CON-
VERSION
INTER-
FACE
16 V
DD
15 CHAN
14 SCLK
13 SDAT
12 CS
THRES-
HOLD
DETECT
&
RESET
11 THR1
10 OVR1
9 RESET
CH1
Pin Description, Digital Interface IC
Symbol
CCLK
CLAT
CDAT
MCLK1
MDAT1
MCLK2
MDAT2
GND
VDD
CHAN
SCLK
SDAT
Description
Clock input for the Serial Configuration Interface (SCI). Serial Configuration data is clocked in on the
rising edge of CCLK.
Latch input for the Serial Configuration Interface (SCI). The last 8 data bits clocked in on CDAT by
CCLK are latched into the appropriate configuration register on the rising edge of CLAT.
Data input for the Serial Configuration Interface (SCI). Serial configuration data is clocked in MSB
first.
Channel 1 Isolated Modulator clock input. Input Data on MDAT1 is clocked in on the rising edge of
MCLK1.
Channel 1 Isolated Modulator data input.
Channel 2 Isolated Modulator clock input. Input Data on MDAT2 is clocked in on the rising edge of
MCLK2.
Channel 2 Isolated Modulator data input.
Digital ground.
Supply voltage (4.5 V to 5.5 V).
Channel select input. The input level on CHAN determines which channel of data is used during the
next conversion cycle. An input low selects channel 1, a high selects channel 2.
Serial clock input. Serial data is clocked out of SDAT on the falling edge of SCLK.
Serial data output. SDAT changes from high impedance to a logic low output at the start of a conver-
sion cycle. SDAT then goes high to indicate that data is ready to be clocked out. SDAT returns to a
high-impedance state after all data has been clocked out and CS has been brought high. SDAT goes
high immediately after RESET is released.
Conversion start input. Conversion begins on the falling edge of CS. CS should remain low during
the entire conversion cycle and then be brought high to conclude the cycle.
Continuous, programmable-threshold detection for channel 1 input data. A high level output on
THR1 indicates that the magnitude of the channel 1 input signal is beyond a user programmable
threshold level between 160 mV and 310 mV. This signal continuously monitors channel 1 indepen-
dent of the channel select (CHAN) signal.
High speed continuous over-range detection for channel 1 input data. A high level output on OVR1
indicates that the magnitude of the channel 1 input is beyond full-scale. This signal continuously
monitors channel 1 independent of the CHAN signal.
Master reset input. A logic high input for at least 100 ns asynchronously resets all configuration reg-
isters to their default values and zeroes the Offset Calibration registers.
CS
THR1
OVR1
RESET
2
Ordering Information
Option
Part number
HCPL-0872
RoHS
Compliant
-000E
Non-RoHS
Compliant
No option
Package
SO-16
Surface
Mount
X
Tape
& Reel
Quantity
47 per tube
-500E
-500
X
X
1000 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
HCPL-0872-500E to order product of 16-Pin SO package in Tape and Reel packaging in RoHS compliant.
Example 2:
HCPL-0872 to order product of 16-Pin SO package in tube packaging and non-RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and
RoHS compliant option will use ‘-XXXE’.
Package Outline Drawings
Standard 16-pin SO Package
PIN NO. 1 IDENTIFIER
∅
1.27 (0.050) x 0.075 (0.003) DEPTH
SHINY SURFACE
16 15 14 13 12 11 10 9
TOP VIEW
BOTTOM VIEW
1.90
(0.075)
1.90
(0.075)
∅
1.27 (0.050)
x 0.075 (0.003)
DEPTH
(2x) EJECTOR PIN
SHINY SURFACE
0.33 x 45
˚
(0.013 x 45
˚
)
7.544 ± 0.05
(0.297 ± 0.002)
A 0872
YYWW
10.00-10.65
(0.394-0.419)
(TIP TO TIP)
TH
XX
1.27
(0.050)
1
2
3
4
5
6
7
8
1.27 (0.050)
SIDE VIEW
1.016 ± 0.025
(0.040 ± 0.001)
7
˚
2.286
(0.090)
1.27 BSC
(0.050 BSC)
0.33-0.51
(0.013-0.020)
R 0.18 (R 0.007)
ALL CORNERS
AND EDGES
0.10-0.30
(0.004-0.0118)
PARTING
LINE
0.01 (0.004)
SEATING PLANE
10.21 ± 0.10
(0.402 ± 0.002)
2.386-2.586
(0.094-0.1018)
A
0.23-0.32
(0.0091-0.0125)
1.016 REF.
(0.040)
END VIEW
DIMENSIONS IN MILLIMETERS (INCHES).
TOLERANCES
(UNLESS OTHERWISE SPECIFIED):
xx.xx = ± 0.010
xx.xxx = ± 0.002
0
˚
- 8
˚
0.40 - 1.27
(0.016 - 0.050)
DETAIL A
3
Solder Reflow Temperature Profile
300
PREHEATING RATE 3˚C + 1˚C/-0.5˚C/SEC.
REFLOW HEATING RATE 2.5˚C ± 0.5˚C/SEC.
PEAK
TEMP.
245˚C
PEAK
TEMP.
240˚C
200
TEMPERATURE (˚C)
160˚C
150˚C
140˚C
PEAK
TEMP.
230˚C
2.5˚C ± 0.5˚C/SEC.
30
SEC.
30
SEC.
SOLDERING
TIME
200˚C
3˚C + 1˚C/-0.5˚C
100
PREHEATING TIME
150˚C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
0
50
100
TIME (SECONDS)
150
200
250
Recommended Pb-Free IR Profile
tp
T
p
TEMPERATURE (˚C)
T
L
T
smax
T
smin
t
s
PREHEAT
60 to 180 SEC.
25
t 25˚C to PEAK
TIME (SECONDS)
NOTES:
THE TIME FROM 25 C to PEAK TEMPERATURE = 8 MINUTES MAX.
T
smax
= 200˚C, T
smin
= 150˚C
t
L
60 to 150 SEC.
260 +0/-5˚C
217˚C
RAMP-UP
3˚C/SEC. MAX.
150 - 200
˚C
RAMP-DOWN
6˚C/SEC. MAX.
TIME WITHIN 5˚C of ACTUAL
PEAK TEMPERATURE
20-40 SEC.
4
Absolute Maximum Ratings
Parameter
Storage Temperature
Operating Temperature
Supply Voltage
Input Voltage
Output Voltage
Lead Solder Temperature
Solder Reflow Temperature Profile
Symbol
Min.
Max.
Units
T
S
-55
125
°C
T
A
-40
85
°C
V
DD
0
5.5
V
All Inputs
-0.5
V
DD
+ 0.5
V
All Outputs -0.5
V
DD
+ 0.5
V
260°C for 10 sec., 1.6 mm below seating plane
See Reflow Thermal Profile
Note
1
Notes 1. Avago Technologies recommends the use of non-chlorinated solder fluxes.
Recommended Operating Conditions
Parameter
Ambient Operating Temperature
Supply Voltage
Input Voltage
Symbol
T
A
V
DD
All Inputs
Min.
-40
4.5
0
Max.
85
5.5
V
DD
Units
°C
V
V
Electrical Specifications (DC)
Unless otherwise noted, all Typical specifications are at T
A
= 25°C and V
DD
= 5 V, and all Minimum and Maximum
specifications apply over the following ranges: T
A
= -40°C to +85°C and V
DD
= 4.5 to 5.5 V.
Parameter
Symbol Min.
Typ.
Max.
Units Test Conditions
Fig.
Supply Current
I
DD
3
5
mA
f
CLK
= 10 MHz
DC Input Current
I
IN
0.001
10
µA
Input Logic Low Voltage
V
IL
0.8
V
Input Logic High Voltage
V
IH
3.6
V
Output Logic Low Voltage
V
OL
0.15
0.4
V
I
OUT
= 4 mA
Output Logic High Voltage
V
OH
4.3
5.0
V
I
OUT
= -400 µA
Clock Frequency
f
CLK
20
MHz
(CCLK, MCLK and SCLK)
Clock Period (CCLK, MCLK and SCLK)
t
PER
50
ns
2, 3
Clock High Level Pulse Width
t
PWH
20
ns
2, 3
(CCLK, MCLK and SCLK)
Clock Low Level Pulse Width
t
PWL
20
ns
2, 3
(CCLK, MCLK and SCLK)
Setup Time from DAT to Rising Edge
t
SUCLK
10
ns
2
of CLK (CDAT, CCLK, MDAT and MCLK)
DAT Hold Time after Rising Edge
t
HDCLK
10
ns
2
of CLK (CDAT, CCLK, MDAT and MCLK)
Setup Time from Falling Edge
t
SUCL1
20
ns
2
of CLAT to First Rising Edge of CCLK
Setup Time from Last Rising
t
SUCL2
20
ns
2
Edge of CCLK to Rising Edge of CLAT
Delay Time from Falling
t
DSDAT
15
ns
3
Edge of SCLK to SDAT
Setup Time from Data
t
SUS
200
ns
3
Ready to First Falling Edge of SCLK
Setup Time from CHAN
t
SUCHS
20
ns
to falling edge of CS
Reset High Level Pulse Width
t
PWR
100
ns
Notes:
1. Avago Technologies recommends the use of non-chlorinated solder fluxes.
5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
