256K x 36, 512K x 18
2.5V Synchronous ZBT SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs
Features
u
256K x 36, 512K x 18 memory configurations
u
Supports high performance system speed - 150 MHz
u
ZBT
TM
Feature - No dead cycles between write and read
u
Internally synchronized output buffer enable eliminates the
u
Single R/W (READ/WRITE) control pin
u
Positive clock-edge triggered address, data, and control
u
u
u
u
u
u
u
need to control
OE
cycles
(3.8 ns Clock-to-Data Access)
Preliminary
IDT71T65602
IDT71T65802
Description
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW
1
-
BW
4
) control (May tie active)
Three chip enables for simple depth expansion
2.5V power supply (±5%)
2.5V I/O Supply (V
DDQ
)
Power down controlled by ZZ input
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA).
The IDT71T65602/5802 are 2.5V high-speed 9,437,184-bit
(9 Megabit) synchronous SRAMs. They are designed to eliminate dead
bus cycles when turning the bus around between reads and writes, or
writes and reads. Thus, they have been given the name ZBT
TM
, or Zero
Bus Turnaround.
Address and control signals are applied to the SRAM during one
clock cycle, and two cycles later the associated data cycle occurs, be it
read or write.
The IDT71T65602/5802 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable
CEN
pin allows operation of the IDT71T65602/5802
to be suspended as long as necessary. All synchronous inputs are ignored
when (CEN) is high and the internal device registers will hold their previous
values.
There are three chip enable pins (CE
1
, CE
2
,
CE
2
) that allow the
user to deselect the device when desired. If any one of these three is not
asserted when ADV/LD is low, no new memory operation can be initiated.
Pin Description Summary
A
0
-A
18
CE
1
, CE
2
,
CE
2
OE
R/W
CEN
BW
1
,
BW
2
,
BW
3
,
BW
4
CLK
ADV/LD
LBO
TMS
TDI
TCK
TDO
ZZ
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
V
DD
, V
DDQ
V
SS
Address Inputs
Chip Enables
Output Enable
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
Advance burst address / Load new address
Linear / Interleaved Burst Order
Test Mode Select
Test Data Input
Test Clock
Test Data Output
Sleep Mode
Data Input / Output
Core Power, I/O Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
N/A
N/A
N/A
N/A
Asynchronous
Synchronous
Static
Static
5302 tbl 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
NOVEMBER 2000
DSC-5302/02
1
©2000 Integrated Device Technology, Inc.
IDT71T65602, IDT71T65802, 256K x 36, 512K x 18, 2.5V Synchronous ZBT SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Range
Description (cont.)
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state two cycles after the chip is deselected or a write
is initiated.
The IDT71T65602/5802 have an on-chip burst counter. In the burst
mode, the IDT71T65602/5802 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the
LBO
input pin. The
LBO
pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
external address (ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH).
The IDT71T65602/5802 SRAMs utilize IDTs latest high-performance
2.5V CMOS process, and are packaged in a JEDEC Standard 14mm x
20mm 100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid
array (BGA) and a 165 fine pitch ball grid array (fBGA).
Pin Definitions
(1)
Symbol
A
0
-A
18
ADV/LD
Pin Function
Address Inputs
Advance / Load
I/O
I
I
Active
N/A
N/A
Description
Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,
ADV/LD low,
CEN
low, and true chip enables.
ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it is
sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip deselected,
any burst in progress is terminated. When ADV/LD is sampled high then the internal burst counter is advanced
for any burst that was in progress. The external addresses are ignored when ADV/LD is sampled high.
R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access
to the memory array. The data bus activity for the current cycle takes place two clock cycles later.
Synchronous Clock Enable Input. When
CEN
is sampled high, all other synchronous inputs, including clock are
ignored and outputs remain unchanged. The effect of
CEN
sampled high on the device outputs is as if the low
to high clock transition did not occur. For normal operation,
CEN
must be sampled low at rising edge of clock.
Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write cycles
(when R/W and ADV/LD are sample d low) the appropriate byte write signal (BW
1
-BW
4
) must be valid. The byte
write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/
W
is sampled
high. The appropriate byte(s) of data are written into the device two cycles later.
BW
1
-BW
4
can all be tied low if
always doing write to the entire 36-bit word.
Synchronous active low chip enable.
CE
1
and
CE
2
are used with CE
2
to enable the IDT71T65602/5802 (CE
1
or
CE
2
sampled high or CE
2
sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle.
The ZBT
TM
has a two cycle de select, i.e., the data bus will tri-state two clock cycles after deselect is initiated.
Synchronous active high chip enable. CE
2
is used with
CE
1
and
CE
2
to enable the chip. CE
2
has inverted polarity
but otherwise identical to
CE
1
and
CE
2
.
This is the clock input to the IDT71T65602/5802. Except for
OE,
all timing references for the device are made with
respect to the rising edge of CLK.
Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and triggered
by the rising edge of CLK.
Burst order selection input. When
LBO
is high the Interleaved burst sequence is sele cted. When
LBO
is low the
Linear burst sequence is selected.
LBO
is a static input and it must not change during device operation.
Asynchronous output enable.
OE
must be low to read data from the 71T65602/5802. When
OE
is high the I/O pins
are in a high-imped ance state.OE does not need to be actively controlled for read and write cycles. In normal
operation,
OE
can be tied low.
Gives input command for TAP controller. Sampled on rising edge of TDK.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK.
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK, while
test outputs are driven from the falling edge of TCK.
Serial outout of registers placed between TDI and TDO. This outout is active depending on the state of the TAP
controller.
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71T65602/5802 to
its lowest power consumption level. Data retention is guaranteed in Sleep Mode.
2.5V core power supply.
2.5V I/O Supply.
Ground.
5302 tbl 02
R/W
CEN
Read / Write
Clock Enable
I
I
N/A
LOW
BW
1
-BW
4
Individual Byte
Write Enables
I
LOW
CE
1
,
CE
2
Chip Enables
I
LOW
CE
2
CLK
I/O
0
-I/O
31
I/O
P1
-I/O
P4
LBO
OE
Chip Enable
Clock
Data Input/Output
Linear Burst Order
Output Enable
I
I
I/O
I
I
HIGH
N/A
N/A
LOW
LOW
TMS
TDI
TCK
TDO
ZZ
V
DD
V
DDQ
V
SS
Test Mode Select
Test Data Input
Test Clock
Test Data Output
Sleep Mode
Power Supply
Power Supply
Ground
I
I
I
O
I
N/A
N/A
N/A
N/A
N/A
N/A
N/A
HIGH
N/A
N/A
N/A
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
2
IDT71T65602, IDT71T65802, 256K x 36, 512K x 18, 2.5V Synchronous ZBT SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Range
Functional Block Diagram
B8E
Address A [0:17]
D
Q
256Kx36 BIT
MEMORY ARRAY
Address
9;
1, CE2,
9;
2
R/
M
Input Register
9;D
ADV/
B:
8M
x
D
Q
Control
DI
DO
D
Clk
Q
Control Logic
Mux
Sel
D
Clk
Clock
Output Register
Q
E;
Gate
5302 drw 01
,,
Data I/O [0:31],
I/O P[1:4]
B8E
Address A [0:18]
D
Q
512Kx18 BIT
MEMORY ARRAY
Address
9;
1, CE2,
9;
2
R/
M
Input Register
9;D
ADV/
B:
8M
x
D
Q
Control
DI
DO
D
Clk
Q
Control Logic
Mux
Sel
D
Clk
Clock
Output Register
Q
E;
Gate
5302 drw 01b
,
,
Data I/O [0:15],
I/O P[1:2]
6.42
3
IDT71T65602, IDT71T65802, 256K x 36, 512K x 18, 2.5V Synchronous ZBT SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Range
Recommended DC Operating
Conditions
Symbol
V
DD
V
DDQ
V
SS
V
IH
V
IH
V
IL
Parameter
Core Supply Voltage
I/O Supply Voltage
Ground
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
Min.
2.375
2.375
0
1.7
1.7
-0.3
(1)
Typ.
2.5
2.5
0
____
____
____
Recommended Operating
Temperature and Supply Voltage
Max.
2.625
2.625
0
Unit
V
V
V
V
V
V
5302 tbl 03
Grade
Commercial
Temperature
(1)
0°C to +70°C
V
SS
0V
V
DD
2.5V±5%
V
DDQ
2.5V±5%
5302 tbl 05
NOTE:
1. T
A
is the instant on case temperature.
V
DD
+0.3
V
DDQ
+0.3
0.7
NOTE:
1. V
IL
(min.) = 0.8V for pulse width less than t
CYC
/2, once per cycle.
A
6
A
7
CE
1
CE
2
BW
4
BW
3
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
NC
(2)
Pin Configuration 256K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/O
P3
I/O
16
I/O
17
V
DDQ
V
SS
I/O
18
I/O
19
I/O
20
I/O
21
V
SS
V
DDQ
I/O
22
I/O
23
V
DD
(1)
V
DD
V
DD
(1)
V
SS
I/O
24
I/O
25
V
DDQ
V
SS
I/O
26
I/O
27
I/O
28
I/O
29
V
SS
V
DDQ
I/O
30
I/O
31
I/O
P4
A
17
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O
P2
I/O
15
I/O
14
V
DDQ
V
SS
I/O
13
I/O
12
I/O
11
I/O
10
V
SS
V
DDQ
I/O
9
I/O
8
V
SS
V
DD
(1)
V
DD
ZZ
I/O
7
I/O
6
V
DDQ
V
SS
I/O
5
I/O
4
I/O
3
I/O
2
V
SS
V
DDQ
I/O
1
I/O
0
I/O
P1
5302 drw 02
,
LBO
A
5
A
4
A
3
A
2
A
1
A
0
DNU
(3)
DNU
(3)
V
SS
V
DD
DNU
(3)
DNU
(3)
Top View
TQFP
NOTES:
1. Pins 14, 16, and 66 do not have to be connected directly to V
DD
as long as the input voltage is
≥
V
IH
.
2. Pin 84 is reserved for a future 16M.
3. DNU = Do not use. Pins 38, 39, 42 and 43 are reserved for respective JTAG pins TMS, TDI, TDO and TCK. Within the current version these pins can be left
unconnected, tied LOW (V
SS
), or tied HIGH (V
DD
).
6.42
4
A
10
A
11
A
12
A
13
A
14
A
15
A
16
IDT71T65602, IDT71T65802, 256K x 36, 512K x 18, 2.5V Synchronous ZBT SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Range
Pin Configuration 512K x 18
A
6
A
7
CE
1
CE
2
NC
NC
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
NC
(2)
A
18
A
8
A
9
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
V
TERM
(3,6)
V
TERM
(4,6)
V
TERM
(5,6)
T
A
(7)
T
BIAS
T
STG
P
T
I
OUT
Rating
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Commercial
-0.5 to +3.6
-0.5 to V
DD
-0.5 to V
DD
+0.5
-0.5 to V
DDQ
+0.5
0 to +70
-55 to +125
-55 to +125
2.0
50
Unit
V
V
V
V
o
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
NC
V
DDQ
V
SS
NC
NC
I/O
8
I/O
9
V
SS
V
DDQ
I/O
10
I/O
11
V
DD
(1)
V
DD
V
DD
(1)
V
SS
I/O
12
I/O
13
V
DDQ
V
SS
I/O
14
I/O
15
I/O
P2
NC
V
SS
V
DDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
10
NC
NC
V
DDQ
V
SS
NC
I/O
P1
I/O
7
I/O
6
V
SS
V
DDQ
I/O
5
I/O
4
V
SS
V
DD
(1)
V
DD
ZZ
I/O
3
I/O
2
V
DDQ
V
SS
I/O
1
I/O
0
NC
NC
V
SS
V
DDQ
NC
NC
NC
5302 drw 02a
C
C
C
o
o
W
mA
5302 tbl 06
,
NOTES:
1. Pins 14, 16, and 66 do not have to be connected directly to V
DD
as long as
the input voltage is
≥
V
IH
.
2. Pin 84 is reserved for a future 16M.
3. DNU = Do not use. Pins 38, 39, 42 and 43 are reserved for respective
JTAG pins: TMS, TDI, TDO and TCK. Within the current version these
pins can be left unconnected, tied LOW (V
SS
), or tied HIGH (V
DD
).
Top View
TQFP
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
DD
terminals only.
3. V
DDQ
terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed V
DDQ
during power
supply ramp up.
7. T
A
is the instant on case temperature.
LBO
A
5
A
4
A
3
A
2
A
1
A
0
DNU
(3)
DNU
(3)
V
SS
V
DD
DNU
(3)
DNU
(3)
TQFP Capacitance
(1)
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
(1)
A
11
A
12
A
13
A
14
A
15
A
16
A
17
BGA Capacitance
(1)
(T
A
= +25°C, f = 1.0MHz)
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
5
7
Unit
pF
pF
5302 tbl 07
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
7
7
Unit
pF
pF
5302 tbl 07a
fBGA Capacitance
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
(T
A
= +25°C, f = 1.0MHz)
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
TBD
TBD
Unit
pF
pF
5302 tbl 07b
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.42
5
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