DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µ
PC8105GR
400 MHz QUADRATURE MODULATOR
FOR DIGITAL MOBILE COMMUNICATION
DESCRIPTION
The
µ
PC8105GR is a sillicon monolithic integrated circuit designed as quadrature modulator for digital mobile
communication systems. This modulator housed in a 16 pin plastic SSOP that is easy to install and contributes to
miniaturizing the system.
The device has power save function and can operates 2.7 to 5.5 V supply voltage to realize low power
consumption.
FEATURES
•
•
•
•
•
Internal 90° phase shifter is accurate over an IF range from 100 MHz to 400 MHz.
Wide supply voltage range: V
CC
= 2.7 to 5.5 V.
Low operation current: I
CC
= 16 mA (typ.).
16 pin plastic SSOP suitable for high density surface mounting.
Low current in sleep mode
APPLICATION
•
•
IF modulator for Digital cellular phone (PDC, IS-54, GSM etc..)
IF modulator for Digital cordless phone (PHS, PCS etc..)
ORDERING INFORMATION
PART NUMBER
PACKAGE
16 pin plastic SSOP (225 mil)
SUPPLYING FORM
Carrier tape width 12 mm. Q’ty 2.5 kp/Reel
Pin 1 indicated pull-out direction of tape.
µ
PC8105GR-E1
To order evaluation samples, please contact your local NEC sales office.
(Part number for sample order:
µ
PC8105GR)
Caution electro-static sensitive device
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. P10807EJ3V0DS00 (3rd edition)
Date Published October 1999 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1995, 1999
µ
PC8105GR
SERIES PRODUCTS
PART
NUMBER
f LO1 in
(MHz)
100 to
300
f MODout
(MHz)
50 to 150
f I/Q
(MHz)
DC to 0.5
Up-Converter
f RFout (MHz)
External
SERIES TYPE
150 MHz Quadrature MOD
Up-Con
+
Quadrature MOD
400 MHz Quadrature MOD
APPLICATIONS
CT2, Digital Comm.
µ
PC8101GR
µ
PC8104GR
µ
PC8105GR
100 to 400
100 to 400
DC to 10
DC to 10
800 to 1900
External
Digital Comm.
Digital Comm.
Remark:
As for detail information of series products, please refer to each data sheet.
INTERNAL BLOCK DIAGRAM AND PIN CONNECTIONS (Top View)
LO
in
1
LO
in
2
GND 3
I-INPUT 4
I-INPUT 5
Q-INPUT 6
Q-INPUT 7
GND 8
90˚
Phase
Sifter
REG.
16 V
CC
15 Power Save
14 GND
13 GND
12 MOD
out
11 N.C.
10 N.C.
9 N.C.
APPLICATION EXAMPLE
[Digital cellular hand-held phone]
Low-noise transistor
RX
DEMO
I
Q
VCO
SW
÷N
PLL
PLL
µ
PC8105GR
I
0˚
TX
PA
Phase
shifter
µ
PC8106T
90˚
Q
2
Data Sheet P10807EJ3V0DS00
µ
PC8105GR
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage
Power Save Voltage
Power Dissipation
Operating Temperature
Storage Temperature
SYMBOL
V
CC
V
PS
P
D
T
op
T
stg
RATING
6.0
6.0
310
−40
to +85
−55
to +150
UNIT
V
V
mW
°C
°C
TEST CONDITIONS
T
A
= +25
°C
T
A
= +25
°C
T
A
= +85
°C
*1
*1:
Mounted on 50
×
50
×
1.6 mm double copper clad epoxy glass board
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Operating Temperature
Modulator Output Frequency
LO1 Input Frequency
I/Q Input Frequency
SYMBOL
V
CC
T
A
f
MODout
f
LO1in
f
I/Qin
DC
10
MHz
MIN.
2.7
−40
100
TYP.
3.0
+25
MAX.
5.5
+85
400
UNIT
V
°C
MHz
P
LOin
=
−10
dBm
P
I/Qin
= 600 mV
p-p
MAX (Single ended)
TEST CONDITIONS
ELECTRICAL CHARACTERISTICS (T
A
= +25
°
C, V
CC
= 3.0 V, Unless Otherwise Specified VPS
≥
1.8 V)
PARAMETER
Circuit Current
Circuit Current at Power
Save Mode
Output Power
LO Carrier Leak
Image Rejection
(Side Band Leak)
SYMBOL
I
CC
I
CC
(PS)
−21.0
MIN.
10
TYP.
16
0.1
−16.5
−40
−40
MAX.
21
5
−12.0
−30
−30
UNIT
mA
TEST CONDITIONS
No input signal
V
PS
≤
1.0 V
µ
A
dBm
dBc
dBc
P
MODout
LOL
ImR
I/Q DC = 1.5 V
P
I/Qin
= 500 mV
p-p
(Single ended)
Data Sheet P10807EJ3V0DS00
3
µ
PC8105GR
STANDARD CHARACTERISTICS FOR REFERENCE
(T
A
= +25
°
C, V
CC
= 3.0 V, Unless Otherwise Specified VPS
≥
1.8 V)
PARAMETER
I/Q 3rd Order
Intermodulation Distortion
I/Q Input Impedance
I/Q Bias Current
LO1 Input VSWR
Power Save Rise Time
Power Save Fall Time
SYMBOL
IM
3I/Q
MIN.
TYP.
−50
MAX.
−30
UNIT
dBc
TEST CONDITIONS
I/Q DC = 1.5 V
P
I/Qin
= 500 mV
p-p
(Single ended)
I/Q DC = 1.5 V
P
I/Qin
= 500 mV
p-p
(Single ended)
(I
→
I, Q
→
Q)
Z
I/Q
I
I/Q
Z
LO
T
PS(RISE)
T
PS(FALL)
20
5
1.2:1
2
2
5
5
kΩ
µ
A
−
µ
s
µ
s
V
PS
(OFF)
→
V
PS
(ON)
V
PS
(ON)
→
V
PS
(OFF)
4
Data Sheet P10807EJ3V0DS00
µ
PC8105GR
PIN EXPLANATION
ASSIGN-
MENT
LOin
SUPPLY
VOL. (V)
−
PIN
VOL.(V)
0
PIN NO.
1
FUNCTION AND APPLICATION
LO input for phase shifter.
This input impedance is 50
Ω
matched internally.
Bypass of LO input.
This pin is grounded through
internal capacitor.
Open in case of single ended.
Connect to the ground with
minimum inductance.
Track length should be kept as
short as possible.
Input for I signal. This in put
impedance is larger than 20 kΩ.
Relations between amplitude and
V
CC
/2 bias of input signal are
following.
V
CC
/2 (v)
≥
1.35
≥
1.5
≥
1.75
Amp. (mV
p-p
)
*1
400
600
1000
4
EQUIPMENT CIRCUIT
1
50
Ω
2
LOin
−
2.4
2
3
GND
0
−
8
−
4
I
V
CC
/2
5
5
I
V
CC
/2
−
Input for I signal. This in put
impedance is larger than 20 kΩ.
V
CC
/2 biased DC signal should be
input.
Input for Q signal. This in put
impedance is larger than 20 kΩ.
V
CC
/2 biased DC signal should be
input.
Input for Q signal. This in put
impedance is larger than 20 kΩ.
Relations between amplitude and
V
CC
/2 bias of input signal are
following.
V
CC
/2 (v)
≥
1.35
≥
1.5
≥
1.75
Amp. (mV
p-p
)
*1
400
600
1000
6
Q
V
CC
/2
−
7
Q
V
CC
/2
−
7
6
12
MODout
−
1.5
Output from modulator.
This is emitter follower output.
12
*1:
In case of that I/Q input signals are single ended.
Of course, I/Q signal inputs can be used either single endedly or differentially with proper terminations.
Data Sheet P10807EJ3V0DS00
5
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