MOS INTEGRATED CIRCUIT
µ
PD16310
HIGH VOLTAGE CMOS DRIVER FOR PDP, EL, VFD
DESCRIPTION
µ
PD16310 is high voltage driver for PDP, EL or VFD graphic panel structured by CMOS process. Logic power
supply is 5.0 V connecting direct to control logic. Maximum output voltage is 80 V and maximum current is 50 mA.
FEATURES
• 80 V Output Voltage Swing Capability
• 50 mA Output Sink and Source Current Capability
• 40 bit Shift-register and Latch
• High Speed Serial DATA Transferring (f
max
. = 20 MHz
• Low Standby Current 100
µ
A
MIN
.)
ORDERING INFORMATION
Part Number
Package
80-pin plastic QFP (3 direction lead)
µ
PD16310GF-3L9
Document No. IC-2859 (1st edition)
Date Published March 1997 P
Printed in Japan
©
1993
µ
PD16310
PIN CONNECTION DIAGRAM (Top View)
O
1
O
2
O
3
O
4
O
5
O
6
O
7
O
8
O
9
O
10
O
11
O
12
O
13
O
14
O
15
O
16
O
17
O
18
O
19
O
20
V
DD2
V
SS2
V
SS2
V
SS1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
O
40
O
39
O
38
O
37
O
36
O
35
O
34
O
33
O
32
O
31
O
30
O
29
O
28
O
27
O
26
O
25
O
24
O
23
O
22
O
21
V
DD2
V
SS2
V
SS2
V
SS1
R/L
V
DD1
PC
NC
NC
A
CLK
NC
NC
NC
B
STB
BLK
NC
V
DD1
Note
The 33 pin (NC) should be open.
All the power supply terminals should be used.
V
SS1
and V
SS2
should be respectively connected with themselves outside.
To prevent latch up breakdown, the power should be turned ON in order V
DD1
, logic input, V
DD2
.
It should be turned OFF in the opposite order.
This relationship should be followed during transition period as well.
2
NC
µ
PD16310
BLOCK DIAGRAM
PC
BLK
STB
O
1
L
1
S
1
A
A
STB
CLK
CLK
R/L
R/L
B
B
S
40
L
40
*
O
40
40 bit
Shift Register
40 bit Latch
*
High Voltage CMOS Driver
80 V ± 50 mA
MAX
.
3
µ
PD16310
PN CONFIGURATION
PIN No.
27
37
36
30
SYMBOL
PC
BLK
STB
A
PIN NAME
Polarity Change Input
Blank Input
Latch Strobe Input
Right Data Input/Output
FUNCTION
All driver outputs’ level are inverted while PC is L.
All driver outputs are H or L while BLK is H.
Latch’s status is data through while STB is L.
R/L = H : A = IN, B = OUT
R/L = L : A = OUT, B = IN
35
31
B
CLK
Left Data Input/Output
Clock Input
Data of shift-register is shifted while CLK is going
H to L. (Negative edge is active.)
H: Right Shift Mode
A
→
O
1
··· O
40
→
B
L: left Shift Mode
B
→
O
40
··· O
1
→
A
High voltage output 80 V, 50 mA
5.0 V
±
10 %
10 to 70 V
Connect to the system ground.
Connect to the system ground.
No. 33 pin should be open.
25
R/L
Shift Direction Control Input
1 - 20
45 - 64
26, 39
21, 44
24, 41
22, 23, 42, 43
28, 29, 32 - 34
38, 40
O
1
- O
40
Driver Outputs
V
DD1
V
DD2
V
SS1
V
SS2
NC
Logic Power Supply
Driver Power Supply
Ground (for Logic)
Ground (for Driver)
No Connect
TRUTH TABLE 1 (Shift-Register part)
INPUT
R/L
H
H
L
L
CLK
↓
H or L
↓
H or L
A
IN
IN
OUT
OUT
IN/OUT
SHIFT-REGISTER
B
OUT
OUT
IN
IN
DATA is shifted.
No Change.
DATA is shifted.
No Change.
TRUTH TABLE 2 (Latch, Driver part)
INPUT
DRIVER OUTPUT
A (B)
X
X
H
H
L
L
X
X
STB
X
X
L
L
L
L
H
H
BLK
H
H
L
L
L
L
L
L
PC
H
L
H
L
H
L
H
L
ALL H
ALL L
H
L
L
H
Latch’s data output
Latch’s data output (inverting)
X = H or L, H = High Level, L = Low Level
4
µ
PD16310
TIMING CHART
(
A (B)
(INPUT)
) : R/L = L
CLK
S
1
(S
40
)
S
2
(S
39
)
S
3
(S
38
)
STB
BLK
PC
O
1
(O
40
)
O
2
(O
39
)
O
3
(O
38
)
5
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