DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD16314
DOT CHARACTER VFD CONTROLLER/DRIVER
DESCRIPTION
The
µ
PD16314 is a VFD controller/driver capable of displaying a dot matrix VFD. It has 80 anode outputs and 24
grid outputs. A single
µ
PD16314 can display up to 16C x 2L, 20C x 2L, or 24C x 2L. The
µ
PD16314 has character
generator ROM in which 248 x 5 x 8 dot characters are stored.
FEATURES
•
Dot matrix VFD controller/driver
•
Capable of driving anodes for cursor display (48 units)
•
80 x 8 bits display RAM incorporated
•
Capable of alphanumeric and symbolic display through internal ROM (5 by 8 dots)
240 characters plus 8 user-defined characters
•
Display contents
16 columns by 2(1) rows + 32(16) cursors, 20 columns by 2(1) rows + 40(20) cursors,
or 24 columns by 2(1) rows + 48(24) cursors.
•
Parallel data input/output (switchable between 4 bits and 8 bits) or serial data input/output can be selected.
•
On-chip oscillator
•
Custom ROM supported
ORDERING INFORMATION
Part Number
Package
144-PIN PLASTIC LQFP(FINE PITCH)(20x20), Standard ROM (ROM code: 001)
144-PIN PLASTIC LQFP(FINE PITCH)(20x20), Standard ROM (ROM code: 002)
µ
PD16314GJ-001-8EU
µ
PD16314GJ-002-8EU
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
S13231EJ1V0DS00 (1st edition)
Date Published March 2000 NS CP(K)
Printed in Japan
The mark
•
shows major revised point.
©
1997
µ
PD16314
3.2 Logic system (Microprocessor Interface)
Pin Symbol
RS,STB
Pin Name
Register
select/strobe
Pin No.
13
I/O
I
Output
Description
When Parallel data transfer is selected, this pin is Register
select.
L: Select instruction register(IR).
H: Select data register(DR).
When serial data transfer mode is selected, this pin is the
strobe input. Data can be input when this signal goes L.
Command processing is performed at the rising edge of this
signal.
/CS
E(/RD),
SCK
Chip select
Enable(read)/shift
clock
26
14
I
I
When this pin is L, this device is active.
When M68 parallel data transfer mode is selected (E), this
pin is enabled. Data is written at the falling edge.
When i80 parallel data transfer selected (/RD), this pin is a
read-enable pin. When this pin is L, data is output to the
data bus.
When serial data transfer is selected, this pin is the shift
clock input. Data is written at the rising edge.
R,/W(/WR)
Read/write signal
(write)
12
I
When M68 parallel data transfer mode is selected (R,/W),
this pin is the data transfer select pin.
L: Write
H: Read
When i80 parallel data transfer mode is selected (/WR), this
pin is written a write-enable pin. Data is written at rising
edge of this signal.
When serial data transfer mode is selected this pin is fixed
to H or L.
SI,SO
Serial I/O
15
I/O
CMOS-
3-states
When serial data transfer mode is selected, this pin is used
as an I/O pin.
When parallel data transfer mode is selected, this pin is
fixed to H or L. DB
0
to DB
7
DB
0
- DB
7
Parallel data I/O
16 to 23
I/O
CMOS-
3-states
When parallel data transfer mode is selected, these pins
are used as I/O pins.
When 4-bits transfer mode is selected, DB
4
to DB
7
are
used. Data is transferred starting from the most significant
bit (MSB) and stored sequentially.
/RESET
Reset
7
I
L: Initializes all the internal registers and commands.
Anode and grid outputs are fixed to V
SS2
.
Data Sheet S13231EJ1V0DS00
5
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