DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD16326A
32-BIT FLUORESCENT DISPLAY TUBE DRIVER
The
µ
PD16326A is a fluorescent display tube driver using a high breakdown voltage CMOS process. It consists
of 32-bit bidirectional shift registers, a latch circuit, and a high breakdown voltage CMOS driver block. The logic block
operates on a 5 V power supply designed to be connected directly to a microcontroller (CMOS level input). The driver
block has a 150 V and 20 mA high breakdown voltage output, and both the logic block and driver block consist of CMOS,
allowing operation with low power consumption.
FEATURES
• High breakdown voltage CMOS structure
• High breakdown voltage, high current output (150 V, 20 mA)
• 32-bit bidirectional shift registers on chip
• Data control by transfer clock (external) and latch
• High-speed data transfer capability (f
max
= 8.0 MHz
MIN
)
• Wide operating temperature range (T
A
= –40 to 85 ˚C)
ORDERING INFORMATION
Part Number
Package
44-pin plastic QFP (4-direction leads)
µ
PD16326AGB-3B4
Document No. S11760EJ1V0DS00 (1st edition)
Date Published December 1997 N
Printed in Japan
©
1997
µ
PD16326A
BLOCK DIAGRAM
CLK
A
R/L
32-bit bidirectional shift registers
B
STB
BLK
32-bit latch
O
1
O
2
O
32
PIN CONFIGURATION (Top View)
O
10
35
44
43
42
41
40
39
38
37
36
V
DD2
V
SS2
A
BLK
STB
CLK
V
SS1
R/L
V
DD1
B
V
SS2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
34
O
11
O
1
O
2
O
3
O
4
O
5
O
6
O
7
O
8
O
9
33
32
31
30
29
28
27
26
25
24
23
O
12
O
13
O
14
O
15
O
16
O
17
O
18
O
19
O
20
O
21
O
22
O
32
O
31
O
30
O
29
O
28
O
27
O
26
O
25
O
24
Remark
Be sure to enter the power to V
DD1
, logic signal, and V
DD2
, in that order, and turn off the power in the reverse
order.
2
V
DD2
O
23
µ
PD16326A
PIN DESCRIPTION
Pin Symbol
STB
A
B
CLK
BLK
R/L
Pin Name
Latch strobe input
RIGHT data input
LEFT data input
Clock input
Blanking input
Shift control input
Pin Number
5
3
10
6
4
8
Description
H: Data through L: Data retention
When R/L = H, A: Input B: Output
When R/L = L, A: Output B: Input
Shift is executed on a fall.
H: O
1
to O
32
: ALL “L”
H: Right shift mode A
→
O
1
... O
32
→
B
L: Left shift mode
B
→
O
32
... O
1
→
A
130 V, 20 mA
5 V
±10
%
30 to 130 V
Connected to system GND
Connected to system GND
MAX
O
1
to O
32
V
DD1
V
DD2
V
SS1
V
SS2
High breakdown voltage output
Logic block power supply
Driver block power supply
Logic ground
Driver ground
13 - 44
9
1, 12
5
2, 11
TRUTH TABLE 1 (SHIFT REGISTER BLOCK)
Input
R/L
H
H
L
L
CLK
↓
H or L
↓
H or L
Output
Note 2
Output
Input
A
Output
Shift Register
B
Output
Note 1
Output
Input
Execution of right shift
Retained
Execution of left shift
Retained
Notes 1.
On a clock fall, the data items of S
31
are shifted to S
32
, and output from B.
2.
On a clock fall, the data items of S
2
are shifted to S
1
, and output from A.
TRUTH TABLE 2 (LATCH BLOCK)
STB
L
H
Operation
Retains S
n
data immediately before STB becomes L.
Outputs shift register data.
TRUTH TABLE 3 (DRIVER BLOCK)
L
n
Note
×
×
L
H
STB
×
L
H
H
BLK
H
L
L
L
Driver output state
L (all driver outputs: L)
Outputs S
n
data on STB fall.
L
H
Note
L
n
: Latch output
Remark
×
= H or L, H = high level, L = Low level
3
µ
PD16326A
ABSOLUTE MAXIMUM RATINGS (T
A
= 25 ˚C, V
SS
= 0 V)
Item
Logic block supply voltage
Driver block supply voltage
Logic block input voltage
Driver block output current
Package allowable power dissipation
Operating ambient temperature
Storage temperature
Symbol
V
DD1
V
DD2
V
I
I
O
P
D
T
A
T
stg
Rating
–0.5 to +7.0
–0.5 to +150
–0.5 to V
DD1
+ 0.5
20
800
Note
–40 to +85
–65 to +150
Unit
V
V
V
mA
mW
˚C
˚C
Note
When T
A
≥
25
°
C, load should be alleviated at a rate of –8.0 mW/
°
C. (T
j
= 125
°
C
(MAX.)
)
RECOMMENDED OPERATING RANGE (T
A
= –40 to +85 ˚C, V
SS
= 0 V)
Item
Logic block supply voltage
Driver block supply voltage
Input voltage high
Input voltage low
Driver output current
Symbol
V
DD1
V
DD2
V
IH
V
IL
I
OH
I
OL
MIN.
4.5
30
0.7·V
DD1
0
TYP.
5.0
MAX.
5.5
130
V
DD1
0.2·V
DD1
–10
+2.5
Unit
V
V
V
V
mA
mA
ELECTRICAL SPECIFICATIONS (T
A
= 25 ˚C, V
DD1
= 4.5 to 5.5 V, V
DD2
= 130 V, V
SS
= 0 V)
Item
Output voltage high
Output voltage low
Output voltage high
Symbol
V
OH1
V
OL1
V
OH21
V
OH22
Output voltage low
Input leakage current
Input voltage high
Input voltage low
Static consumption current
V
OL2
I
IL
V
IH
V
IL
I
DD1
I
DD1
I
DD2
I
DD2
Logic, T
A
= –40 to +85 ˚C
Logic, T
A
= 25 ˚C
Driver, T
A
= –40 to +85 ˚C
Driver, T
A
= 25 ˚C
Condition
Logic, I
OH
= –1.0 mA
Logic, I
OL
= 1.0 mA
O
1
to O
40
, I
OH
= –0.5 mA
O
1
to O
40
, I
OH
= –5.0 mA
O
1
to O
40
, I
OL
= 0.5 mA
V
I
= V
DD1
or V
SS1
0.7·V
DD1
0
MIN.
0.9·V
DD1
0
126
120
2.5
±1.0
V
DD1
0.2·V
DD1
1 000
100
1 000
100
TYP.
MAX.
V
DD1
0.1·V
DD1
Unit
V
V
V
V
V
µ
A
V
V
µ
A
µ
A
µ
A
µ
A
4
µ
PD16326A
SWITCHING CHARACTERISTICS (T
A
= 25 ˚C, V
DD1
= 5.0 V, V
DD2
= 130 V, V
SS
= 0 V, logic C
L
=
15 pF, driver C
L
= 50 pF, driver R
L
= 220 kΩ, t
r
= t
f
= 10 ns)
Item
Transmission delay time
Symbol
t
PHL1
t
PLH1
t
PHL2
t
PLH2
Fall time
Rise time
Maximum clock frequency
Input capacitance
t
THL
t
TLH
f
max
C
I
O
1
to O
32
O
1
to O
32
With cascading, Duty = 50 %
8.0
15
BLK
↓→
O
1
to O
32
CLK
↓→
A/B
Condition
MIN.
TYP.
MAX.
110
110
300
300
600
500
Unit
ns
ns
ns
ns
ns
ns
MHz
pF
TIMING REQUIREMENTS (T
A
= – 40 to +85 ˚C, V
DD1
= 4.5 to 5.5 V, V
SS
= 0 V, t
r
= t
f
= 10 ns)
Item
Clock pulse width
Strobe pulse width
Blank pulse width
Data setup time
Data hold time
Clock-strobe time
Strobe-clock time
Strobe-blank time
Symbol
PW
CLK
PW
STB
PW
BLK
t
setup
t
hold
t
CLK-STB
t
STB-CLK
t
STB-BLK
CLK
↓→
STB
↑
STB
↓→
CLK
↓
STB
↑→
BLK
↓
Condition
MIN.
40
80
1 500
15
30
45
45
80
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
5
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