DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD16337
64-BIT AC-PDP DRIVER
The
µ
PD16337 is a high-voltage CMOS driver designed for flat display panels such as PDPs, VFDs and ELs. It
consists of a 64-bit bi-directional shift register (16 bit
×
4 circuits), 64-bit latch and high-voltage CMOS driver. The
logic block is designed to operate at 5-V power supply, enabling direct connection to a microcontroller. In addition,
the
µ
PD16337 achieves low power dissipation by employing CMOS structure while having a high withstand voltage
output (150 V, 40 mA MAX.)
FEATURES
• Built in four 16-bit bi-directional shift register circuits
• Data control with transfer clock (external) and latch
• High-speed data transfer (f
max.
= 20 MHz MIN. at cascade connection)
• Wide operating temperature range (T
A
= –40 to +85°C)
• High withstand output voltage (150 V, 40 mA MAX.)
• 5-V CMOS input interface
• High withstand voltage CMOS structure
• Capable of reversing all driver outputs by PC pin
ORDERING INFORMATION
Part Number
Package
100-pin plastic QFP
µ
PD16337GF-3BA
Document No. S12363EJ1V0DS00 (1st edition)
Date Published January 1998 N CP(K)
Printed in Japan
©
1998
µ
PD16337
BLOCK DIAGRAM
PC
BLK
LE
SR1
A
1
CLK
R/L
B
1
A
1
CLK
R/L
B
1
S
1
S
5
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S
61
S
1
S
2
S
3
S
4
LE
L
1
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L
64
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Note
O
1
SR2
A
2
A
2
CLK
R/L
B
2
B
2
S
2
S
6
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S
62
SR3
A
3
A
3
CLK
R/L
B
3
B
3
S
3
S
7
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S
63
SR4
A
4
A
4
CLK
R/L
B
4
B
4
S
4
S
8
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S
64
S
61
S
62
S
63
S
64
S
64
SRn: 16-bit shift register
Note
High withstand voltage CMOS driver, 150 V,
±40
mA (MAX.)
2
µ
PD16337
PIN CONFIGURATION (Top View)
O
42
O
41
O
40
O
39
O
38
O
37
O
36
O
35
O
34
O
33
O
32
O
31
O
30
O
29
O
28
O
27
O
26
O
25
O
24
O
23
80
79
78
77
76
75
74
73
72
71
70
69
68
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
V
DD2
NC
V
SS2
NC
O
43
O
44
O
45
O
46
O
47
O
48
O
49
O
50
O
51
O
52
O
53
O
54
O
55
O
56
O
57
O
58
O
59
O
60
O
61
O
62
O
63
O
64
NC
V
DD2
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
NC
V
DD2
NC
V
SS2
NC
O
22
O
21
O
20
O
19
O
18
O
17
O
16
O
15
O
14
O
13
O
12
O
11
O
10
O
9
O
8
O
7
O
6
O
5
O
4
O
3
O
2
O
1
NC
V
DD2
NC
67
14
66
15
100-pin plaxtic QFP
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
V
SS2
NC
CLK
LE
B
4
B
3
B
2
B
1
V
SS1
NC
R/L
V
DD1
A
1
A
2
A
3
A
4
Cautions 1. Pin 40 is connected to the lead frame, and therefore must be left open.
2. Ensure that the V
DD1
, V
DD2
, V
SS1
and V
SS2
pins are all used, and that V
SS1
and V
SS2
are used
at the same potential.
3. To prevent latch up breakdown, the power should be turned on in the order V
DD1
, logic signal,
V
DD2
. It should be turned off in the opposite order.
PC
BLK
NC
V
SS2
3
µ
PD16337
PIN DESCRIPTION
Symbol
PC
BLK
LE
Pin Name
Polarity change input
Blank input
Latch enable input
Pin Number
47
48
34
Description
PC = L: All driver output invert
BLK = H: All output = H or L
Automatically executes latch by setting High at rising edge
of the clock
When R/L = H,
A
1
to A
4
: Input B
1
to B
4
: Output
When R/L = L,
A
1
to A
4
: Output B
1
to B
4
: Input
Shift executed on fall
Right shift mode when R/L = H
SR
1
: A
1
→
S
1
··· S
61
→
B
1
(Same direction for SR
2
·SR
4
)
Left shift mode when R/L = L
SR
1
: B
1
→
S
61
··· S
1
→
A
1
(Same direction for SR
2
·SR
4
)
130 V, 40 mA MAX.
5 V
±10%
30 to 130 V
Connect to system GND
Connect to system GND
Non-connection
Ensure that pin 40 is left open.
A
1
to A
4
RIGHT data input/output
43 to 46
B
1
to B
4
LEFT data input/output
38 to 35
CLK
R/L
Clock input
Shift control input
33
41
O
1
to O
64
High withstand voltage output
54 to 75, 81 to
100, 6 to 27
42
2, 29, 52, 79
39
4, 31, 50, 77
1, 3, 5, 28, 30,
32, 40, 49, 51,
53, 76, 78, 80
V
DD1
V
DD2
V
SS1
V
SS2
NC
Power supply for logic block
Power supply for driver block
Logic GND
Driver GND
Non-connection
4
µ
PD16337
TRUTH TABLE 1 (Shift Register Block)
Input
R/L
H
H
L
L
CLK
↓
H or L
↓
H or L
Output
Note 2
Output
Input
A
Output
Shift Register
B
Output
Note 1
Output
Input
Right shift execution
Hold
Left shift execution
Hold
Notes 1.
The data of S
57
, S
58
, S
59
, S
60
shifts to S
61
, S
62
, S
63
, S
64
and is output from B
1
, B
2
, B
3
, B
4
at the falling
edge of the clock, respectively.
2.
The data of S
5
, S
6
, S
7
, S
8
shifts to S
1
, S
2
, S
3
, S
4
and is output from A
1
, A
2
, A
3
, A
4
at the falling edge of
the clock, respectively.
TRUTH TABLE 2 (Latch Block)
LE
H
CLK
↑
↓
L
×
Output State of Latch Block (L
n
)
Latch S
n
data and hold output data
Hold latch data
Hold latch data
TRUTH TABLE 3 (Driver Block)
L
n
×
×
×
×
BLK
H
H
L
L
PC
H
L
H
L
Output State of Driver Block
H (All driver outputs: H)
L (All driver outputs: L)
Output latch data (L
n
)
Output reversed latch data (L
n
)
×:
H or L, H: High level, L: Low level
5
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