MOS INTEGRATED CIRCUIT
µ
PD16430A
1/2, 1/3, 1/4 DUTY LCD CONTROLLER/DRIVER
The
µ
PD16430A is an LCD controller/driver that enables the display of LCDs of 1/2 duty, 1/3 duty and 1/4 duty
cycle.
The LCD controller contained in the
µ
PD16430A employs serial data transfer and uses an automatic increment
function for data addresses which eliminates the need to set addresses newly each time.
The LCD driver uses a medium voltage output (14 V max.), which enables higher contrast and a wider viewing angle
even with a 1/3 or 1/4 duty cycle.
By using an on-chip drive bias circuit, it is possible to eliminate the need for external resistors.
FEATURES
• LCD direct drive (medium voltage output: 14 V MAX.)
• Choice of 3 duty cycles
1/2 duty, 1/3 duty, 1/4 duty
• Display dot number:
1/2 duty: 120
1/3 duty: 160
1/4 duty: 240
• 2 types of drive bias
1/2 bias, 1/3 bias
• Choice of 4 types of frame frequency
• Multi-chip configuration possible
• Control through 8-bit serial interface
• On-chip power-on reset circuit
• Low-power dissipation CMOS
• 3.5 to 6.0 V logic supply voltage
ORDERING INFORMATION
Part number
Package
80-pin plastic QFP (14
×
20)
µ
PD16430AGF-3B9
Document No. IC-2776 (1st edition)
(O.D. No. IC-8302)
Date Published March 1997 N
Printed in Japan
©
1994
µ
PD16430A
PIN CONFIGURATION (Top View)
V
DD
LCDOFF
BUSY
CLK
V
SS
OSC
OUT
80 7978 77 76 7574 73 72 7170 69 68 6766 65
LCD0
LCD1
LCD2
LCD3
LCD4
LCD5
LCD6
LCD7
LCD8
LCD9
LCD10
LCD11
LCD12
LCD13
LCD14
LCD15
LCD16
LCD17
LCD18
LCD19
LCD20
LCD21
LCD22
LCD23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25 2627 28 29 3031 32 33 3435 36 37 3839 40
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
COM1
COM0
LCD59
LCD58
LCD57
LCD56
LCD55
LCD54
LCD53
LCD52
LCD51
LCD50
LCD49
LCD48
LCD47
LCD46
LCD45
LCD44
LCD43
LCD42
LCD41
LCD40
LCD39
LCD38
LCD24
LCD25
LCD26
LCD27
LCD28
LCD29
LCD30
LCD31
NC
Remark
Be sure to leave Pin 33 open since it is connected to the lead frame.
2
V
SS
LCD32
LCD33
LCD34
LCD35
LCD36
LCD37
OSC
IN
V
LCD
V
LC0
SYNC
DATA
STB
V
LC1
V
LC2
COM3
COM2
µ
PD16430A
PIN FUNCTIONS
No.
1
to
32
35
to
62
Symbol
LCD0
to
LCD31
LCD32
to
LCD59
I/O
Output
Output Type
CMOS
Description
These pins serve as the LCD driver’s segment signal output pins.
The following display modes can be selected for the LCD driver.
Duty
1/2
Bias
1/2
Display
Dot No.
120
Frame frequency (Hz)
(fosc = 140 kHz)
fosc
fosc
fosc
fosc
256 , 512 , 1024 , 2048
(547) (273) (137)
(68)
fosc
fosc
fosc
fosc
384 , 768 , 1536 , 3072
(365) (182)
(91)
(46)
fosc
fosc
fosc
fosc
512 , 1024 , 2048 , 4096
(273) (137)
(68)
(34)
1/3
1/3
160
1/4
1/3
240
A matrix of these segment signal output pins and COM3, COM2, COM1
and COM0 pins enables the maximum display of 240 dots (1/4 duty
selected).
The output voltage of the segment signal output pins is supplied by the
V
LCD
pin.
The output voltage of the segment signal output pin is supplied by dividing
and outputting 0 to V
LCD
voltage using any driving method (any bias
method).
Either internal or external voltage dividing resistor can be selected.
63
to
66
COM0
to
COM3
Output
CMOS
These pins serve as the LCD driver’s common signal output pins.
The LCD driver can select three display modes.
A matrix of these common signal output pins and LCD59 through LCD0
pins enables the maximum display of 240 dots (1/4 duty selected).
The output voltage of the common signal output pins is supplied by the
V
LCD
pin.
V
DD
to 14 V voltage is supplied by this pin.
The output voltage of the common signal output pins is supplied by
dividing and outputting 0 to V
LCD
voltage using any driving method (any
bias method).
Either internal or external dividing resistor can be selected.
67
68
69
70
V
LC2
V
LC1
V
LC0
V
LCD
—
—
These pins serve as the LCD driver’s drive voltage generation pins.
The drive voltage can be set by using either these pins or the on-chip
drive voltage generation circuit, as specified by command data.
This pin supplies the LCD driver’s supply voltage.
V
DD
to 14 V voltage is supplied to this pin.
The output voltage of the segment signal and command signal output pins
is supplied by dividing and outputting the voltage applied to these pins
using any driving method (any bias method).
Do not supply a voltage exceeding V
DD
to the V
LCD
pin before the device’s
supply voltage reaches 3.5 V, as this may cause incorrect display.
—
—
3
µ
PD16430A
No.
71
72
Symbol
OSC
IN
OSC
OUT
I/O
I/O
Output Type
CMOS
Description
These pins serve to connect the resistors of the system clock RC oscillator.
OSC
IN
70
OSC
OUT
71
100 kΩ
When several devices are used, connect as follows:
OSC
IN
70
100 kΩ
34
73
74
V
SS
—
—
GND pin for device.
OSC
OUT
71
OSC
IN
70
OSC
OUT
71
SYNC
I/O
Nch
Open drain
Synchronous signal I/O pin.
This pin is used to synchronize two or more
µ
PD16430A’s. At this time,
each chip must be wire-ORed and a pull-up resistor (5 k to 10 kΩ) is
required.
This pin must be pulled up even when only one
µ
PD16430A is used.
Strobe signal input pin for device’s select signal and serial communica-
tions.
This pin serves to latch display RAM data outputs, set the command data
receive mode and initialize serial communications.
Serial communication is enabled when this signal is a logic low.
When this pin is a logic high, shift clocks that are input are ignored.
(1) Display RAM data output buffer latch function
The internal display RAM data output is latched to the output latch circuit
at the rising edge of the STB signal when the BUSY pin outputs a logic
high.
However, latch timing depends on the LATCH MD and LATCH flags.
The latch time is 504.5/f
OSC
.
When the BUSY signal is a logic low, latching can cause incorrect display.
(2) Command data receive mode setting
The command data receive mode is set by the rising edge of the STB
signal when the BUSY pin outputs a logic high.
Once the command data receive mode is set, the initial byte (8 bits) is
processed as a command.
The command data processing time is approximately 300 ns.
The BUSY signal does not change during this time.
(3) Serial communication is initialized by the rising edge or the falling edge
of the STB signal when the BUSY pin outputs a logic low.
Once serial communication is initialized, the command data receive mode
is started.
During command data decoding or display data RAM interrupt, the STB
signal interrupts processing and initializes serial communications. At this
time, all displays are turned off (LCDON flag is reset).
75
STB
Input
—
76
DATA
Input
—
This pin inputs serial data for serial communication at the rising edge of
the shift clock.
77
CLK
Input
—
This pin inputs a shift clock for serial communication. The signal is output
at the rising edge of the shift clock signal.
4
µ
PD16430A
No.
78
Symbol
BUSY
I/O
Output
Output Type
Nch
Open drain
Description
This pin outputs the serial communication status and the internal data
processing status.
When this signal is a logic high, serial communication is executed.
When this signal is a logic low, it indicates that the display RAM data is
latched to the output buffer.
When the power-on reset circuit is operating, this pin holds a logic low until
a rising or falling signal is input to the STB pin.
79
LCDOFF
Input
—
This pin serves to turn off all the LCD displays.
When a logic low is input to this pin, all LCD displays are turned off.
Display RAM data is maintained.
Since displays are turned off only by the output driver, serial communica-
tions can be executed as usual.
To turn on displays, it is necessary to input a logic high to this pin and
reset the LCDON flag.
This pin is a power supply pin to the device.
A voltage of 3.5 to 6.0 V is supplied to this pin.
When the supply voltage rises from 0 V to 3 V, or when it reaches a value
under 3 V and then rises again, the power-on reset circuit starts operating
and the device is set to its initialized state.
When the device is in its initialized state, all displays are turned off
(segment and common signals are fixed to V
LCD
).
Do not supply a voltage higher than V
DD
to the V
LCD
pin before the supply
voltage reaches 3.5 V as this will cause incorrect display.
80
V
DD
—
—
5
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