DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD16431A
1/2, 1/3, 1/4-DUTY LCD CONTROLLER/DRIVER
The
µ
PD16431A is an LCD controller/driver that enables display of segment type LCDs of 1/2, 1/3, or 1/4 duty
cycle. This controller/driver has 56 segment output lines of which eight can also be used as LED output lines.
Because the LCD driver contained in the
µ
PD16431A has separate logic and power supply, up to 6.5 V of LCD
drive voltage can be set. In addition, key source output lines for key scanning and key input data lines are
also provided, so that the
µ
PD16431A is ideal for applications in the front panel of an automobile stereo system.
FEATURES
• Various display modes
1/2 duty: 112 segment outputs or 96 segment outputs + 8 LED outputs
1/3 duty: 168 segment outputs or 144 segment outputs + 8 LED outputs
1/4 duty: 224 segment outputs or 192 segment outputs + 8 LED outputs
• Key scan circuit (key source outputs are shared with LCD driver outputs)
• Independent LCD driver power supply V
LCD
(can be set to V
DD
to 6.5 V)
• Serial data input/output (SCK, STB, DATA)
• On-chip oscillator incorporated
• Power-ON reset circuit
ORDERING INFORMATION
Part Number
Package
80-pin plastic QFP (0.65 pitch, 14
×
14)
µ
PD16431AGC-7ET
Document No. IC-3414
(O.D. No. IC-8885)
Date Published January 1995 P
Printed in Japan
©
1995
µ
PD16431A
PIN FUNCTIONS
Symbol
SEG
1
/KS
1
to
SEG
8
/KS
8
SEG
9
to SEG
48
SEG
49
/LED
1
to
SEG
56
/LED
8
COM
1
to COM
4
SCK
Name
Segment output/key
source output
Segment output
Segment output/LED
output pins
Common output
Shift clock input
33 to 72
73 to 80
No.
25 to 32
Description
These pins serve as LCD segment output pins and key
source output pins for key scanning.
LCD segment output pins
These pins can be used as LCD segment output or LED
output pins depending on the setting of the LCD/LED pin.
LCD common output pins
Data shift clock. Data is read at the rising edge, and is
output at the falling edge of this clock.
This pin inputs a command or display data, or outputs
key data.
A command or data is input at the rising edge of the shift
clock, starting from the most significant bit. Key data is
output at the falling edge of the shift clock, starting from
the most significant bit.
This pin serves as an open-drain pin in the output mode.
Data can be input when this signal goes low. When it
goes high, command processing is performed.
When this signal goes high, the SEG
n
/LED
m
pins function
as LCD segment output pins; when it goes low, they
function as LED driver output pins. The LED driver has a
drive capability of 15 mA and is N-ch open drain.
OE
Note
21 to 24
7
DATA
Data input/output
8
STB
Strobe input
9
LCD/LED
LCD/LED select
10
Output enable input
11
When this signal goes low, all the segment output and
LED output pins are off (SEG
n
= COM
n
= V
LCD
). Internal
data are saved.
OSC
IN
OSC
OUT
SYNC
Oscillation input
Oscillation output
Synchronizing signal
12
13
14
Connect a resistor for oscillation circuit across these pins.
A synchronizing signal input pin. When two or more
µ
PD16431A’s are used, each device is wired-ORed. This
pin must be pulled up when this chip is used alone.
KEY
1
to KEY
4
KEY REQ
Key data input
Key request output
2 to 5
6
Key data input pins for key scanning
This signal goes high when a key is pressed (key data = H).
Read the key data only while this pin is high.
Power supply pin for internal logic
GND pin for internal logic and LED output
Power supply pin for LCD drive
GND pin for LCD drive
Power supply for driving dot matrix LCD
V
DD
V
SS
V
LCD
V
EE
V
LC1
to V
LC3
Logic power supply
Logic GND
LCD drive power supply
LCD GND
Power supply for LCD
drive
15
1
16
20
17 to 19
Note
At OE = L, the key data cannot be written correctly, even when the display ON/OFF of the status
command is set to the “normal operation” (10). Also, in this state, unnecessary waveforms are
generated from between SEG
1
/KS
1
to SEG
8
/KS
8
during the key scanning period. (The display is OFF.)
4
µ
PD16431A
CONFIGURATION OF SHIFT REGISTER
Two shift registers, an 8-bit command register and a 56-bit display register, are provided. The first 8 bits
of input data are recognized as a command and are sent to the command register, and the 9th bit and those
that follow are recognized as display data and are sent to the display register.
8-bit shift register
MSB
b7
b0
LSB
Command
56-bit shift register
MSB
SEG
56
/LED
8
Display data (LCD, LED)
SEG
1
Transfer direction
LSB
The meaning of the display data is as follows:
LCD: 0
→
off, 1
→
on
LED: 0
→
on, 1
→
off
Be sure to transfer 56 bits of display data.
CONFIGURATION OF OUTPUT LATCH
MSB
SEG
56
/LED
8
SEG
56
/LED
8
SEG
56
/LED
8
SEG
56
/LED
8
LSB
SEG
1
SEG
1
SEG
1
SEG
1
COM
1
(latch address
Note
: 00)
COM
2
(latch address
Note
: 01)
COM
3
(latch address
Note
: 10)
COM
4
(latch address
Note
: 11)
Note
Bits b3 and b4 of status command (Refer to page 8.)
5
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