DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD16454A
The
µ
PD16454A is a single-chip controller/driver for dot matrix LCD, enabling the display of up to 48
alphanumerical and kana characters and symbols (24 characters
×
2 lines) each of which is composed of 5
×
7 dots.
On-chip charge pump-type DC/DC converter that enables the
µ
PD16454A to operate on a single 5-V power supply
and the chip design aiming at tape carrier package (TCP) mounting make the
µ
PD16454A ideal for portable
equipment and all kinds of data terminals for which downsizing is an important consideration.
FEATURES
• 5
×
7 dot matrix LCD display controller/driver
• 24 characters
×
2 lines, 1/14 duty display
• Interface with CPU 4 bits wise
• On-chip ROM and RAM
• Display data RAM (8
×
48 bits)
• Character generator RAM (8 user-defined characters; 5
×
7
×
8 bits)
• Character generator ROM (160 characters; 5
×
7
×
160 bits)
• On-chip LCD driver
• 120 segment signals
• 14 common signals
• Single 5-V power supply
• Doubling DC/DC booster generating 10 V for driving LCDs
• Total power dissipation: 2 mA max.
• On-chip temperature compensation circuit
• TCP mounting enabled
ORDERING INFORMATION
Part number
Available as
TCP (TAB)
Chip
µ
PD16454AN-XXX
µ
PD16454AP
TPC formats are created on a custom-made basis.
representative.
For additional information, contact an NEC sales
For purchases of chips only, additional documents on quality are required. Contact an NEC sales representative.
Document No. IC-3362A (2nd edition)
(0. D. No. IC-8800)
Date Published March 1997 P
Printed in Japan
©
1994
2
Address counter
(AC)
Timing circuit
6
6
6
6
3
Instruc-
tion
decoder
Disply data RAM
(DDRAM)
8
×
48 bits
14-bit
shift
register 14
Common
signal
driver
14
COM
14
COM
1
8
8
8
8
3
3
6
8
8
Character generator RAM
(CGRAM)
5
×
7
×
8 bits
Character generator ROM
(CGROM)
5
×
7
×
160 bits
12-bit
latch
120
Segment
signal
driver
SEG
1
120
SEG
120
120
5
Serializer
(parallel data
→
serial data)
5
120-bit
shift register
BLOCK DIAGRAM
8
8
Instruc-
tion
register
(IR)
CLK
RS
E
DB
0
to DB
3
4
I/O
buffer
8
RESET
Data
register
(DR)
TEST
BF
Busy flag
C (+)
C (−)
DC/DC
converter
V
DD
V
CC1
V
CC2
GND
1
GND
2
V
1
V
2
V
3
V
4
V
5
OP amp.
µ
PD16454A
V
IN
(+)
V
IN
(−)
µ
PD16454A
PIN FUNCTION
Symbol
RS
Pin No.
138
Input/Output
Input
Connect to
CPU
Function
Register selection signal
‘0’ instruction register (IR)
‘1’ data register (DR)
Data reading signal
Reads data at the falling edge.
TEST
140
Input
Test pin
‘1’ = test mode
‘0’ or open = normal operation
CPU
When busy flag is ‘1’, indicates that internal part of
LCD is currently operating.
In test mode, functions as test output.
Data input signals
In test mode, function as output pin.
Reset is performed with reset signal ‘0’
LCD-driving clock
Common signals
Segment signal outputs
LCD-driving supply voltages
Power supply for logic circuits
Power supply for logic circuits
Boosted power supply
Ground for logic circuit
Ground for high-voltage circuit
Reference voltage supply
LCD-driving supply voltage adjustment input
Capacitor
Capaditor
Capacitor connection pin for booster
Capacitor connection pin for booster
E
139
Input
CPU
BF
145
Output
DB
0 to 3
141 to 144
Input/Output
CPU
RESET
CLK
COM
1 to 14
SEG
1 to 120
V
1 to 5
V
CC1
V
CC2
V
DD
GND1
GND2
V
IN
(+)
V
IN
(−)
C (+)
C (−)
137
146
128 to 134, 7 to 1
127 to 68, 8 to 67
153 to 157
148
136
135
147
158
151
152
149
150
Input
Input
Output
Output
CPU
CPU
LCD
LCD
Power supply
Power supply
Power supply
Power supply
Power supply
Power supply
Power supply
3
µ
PD16454A
PIN CONFIGURATION (Pad Configuration)
GND
2
V
5
V
4
V
3
V
2
V
1
V
IN
+
V
IN
−
C
−
C
+
V
CC1
GND
1
CLK
BF
DB
3
DB
2
DB
1
DB
0
TEST
E
RS
RESET
V
CC2
V
DD
COM
14
158
1
135
134
COM
7
COM
8
SEG
61
SEG
62
COM
1
SEG
1
SEG
2
67
68
SEG
119
SEG
120
4
SEG
60
SEG
59
µ
PD16454A
BLOCK FUNCTIONS
(1) Registers (IR, DR)
This LCD contains both an 8-bit instruction register (IR) and an 8-bit data register (DR).
The IR register stores display clear instruction codes and display data RAM (DDRAM) and character generaotor
RAM (CGRAM) addresses.
The DR register temporarily stores data to be transferred to DDRAM and CGRAM.
The IR and DR registers are selected with the register selector (RS) bit.
RS
0
1
Register selector
IR
DR
(2) Busy flag (BF)
When BF = ‘1’, this indicates that the LCD’s internal circuit is currently operating. Therefore, after ascertaining
that BF = ‘0’, it is necessary to read the next instruction or display data.
(3) Address counter (AC)
The AC is a counter that sets addresses in DDRAM and CGRAM. When an address-setting instruction is
written to the IR, the address value is set from the IR to the address counter. At the same time, which of
DDRAM and CGRAM is selected is also determined.
After display data is written in DDRAM or CGRAM, the address counter’s address value is automatically
incremented by 1. Nevertheless, since data in CGRAM consists of 7 bytes characters, the address value is
incremented by 2 only when display data has been written to the 7th line.
(4) Display data RAM (DDRAM)
DDRAM is a RAM that stores display data consisting of 8-bit character codes. The capacity is 8
×
48 bits so
that 48 characters can be stored. The correspondence between DDRAM addresses and display position on
LCD is shown in Fig. 1.
5
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