DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD16641
SOURCE DRIVER FOR 240-OUTPUT TFT-LCD (64 GRAY SCALES)
DESCRIPTION
The
µ
PD16641 is a source driver for TFT-LCD 64 gray scale displays. Its logic circuit operates at 3.3 V and the
driver circuit operates at 3.3 or 5.0 V (selectable). The input data is digital data at 6 bits
×
3 dots, and 260,000 colors
can be displayed in 64-value outputs
γ
-corrected by the internal D/A converter and 11 external power supplies.
Because the clock frequency is 33 MHz
MIN
, the
µ
PD16641 can be used in TFT-LCD panels conforming to the VGA
standards.
FEATURES
• Precharge-less output buffer
• 64-value output by 11 external power supplies and internal D/A converter
• Level of
γ
-corrected power supply can be inverted
• Output voltage range: 2.8 V
P-PMAX.
(at supply voltage V
DD2
of driver circuit = 3.0 V)
4.3 V
P-PMAX.
(at supply voltage V
DD2
of driver circuit = 4.5 V)
• CMOS level input
• 6 bit (gray scale data)
×
3 dot input
• High-speed data transfer: f
max.
= 33 MHz
MIN.
(internal data transfer rate at supply voltage V
DD1
of logic circuit = 3.0 V)
• 240 outputs
• Supply voltage of driver circuit selectable (V
sel
= H: 3.3 V, V
sel
= L: 5.0 V)
• Slim TCP
ORDERING INFORMATION
Part No.
Package
TCP (TAB package)
µ
PD16641N-×××
The TCP is custom-made. For details, consult NEC
Document No. S10565EJ1V0DS00 (1st edition)
Date Published May 1998 N CP(K)
Printed in Japan
©
1998
µ
PD16641
1. BLOCK DIAGRAM
STHR
R/L
CLK
C
1
C
2
STHL
V
DD1
(3.3 V)
V
SS1
C
79
C
80
80-bit bidirectional shift register
D
00 to 05
D
10 to 15
D
20 to 25
Data register
STB
Latch
V
sel
D/A converter
V
0
to V
10
V
DD2
(3.3/5.0 V)
V
SS2
Output buffer
S
1
S
2
S
3
S
240
2
µ
PD16641
2. PIN CONFIGURATION (standard TCP:
µ
PD16641N-×××
×××)
×××
COMMON
COMMON
V
sel
V
SS2
V
DD2
V
10
V
8
V
6
V
4
V
2
V
0
R/L
D
20
D
21
D
22
D
23
D
24
D
25
STB
STHL
V
DD1
CLK
V
SS1
STHR
D
10
D
11
D
12
D
13
D
14
D
15
D
00
D
01
D
02
D
03
D
04
D
05
V
1
V
3
V
5
V
7
V
9
V
DD2
V
SS2
COMMON
Monitor pin
COMMON
COMMON
COMMON
NC
NC
NC
COMMON
COMMON
COMMON
NC
NC
NC
NC
S
240
S
239
(Copper foil
surface)
Monitor pin
S
2
S
1
NC
NC
NC
NC
COMMON
COMMON
COMMON
NC
NC
NC
COMMON
COMMON
COMMON
V
sel
pin is internally pulled up.
Therefore, the number of input pins can be reduced by opening or short-circuiting these pins to V
SS2
by means of
TCP wiring.
3
µ
PD16641
3. PIN DESCRIPTION
Pin Symbol
S
1
to S
240
D
00
to D
05
D
10
to D
15
D
20
to D
25
R/L
Shift direction select input
This pin inputs/outputs start pulses when two or more
µ
PD16641s are connected
in cascade. Shift direction of shift register is as follows:
R/L = H : STHR input, S
1
→
S
240
, STHL output
R/L = L : STHL input, S
240
→
S
1
, STHR output
R/L = H : Inputs start pulse.
R/L = L : Outputs start pulse.
R/L = H : Outputs start pulse.
R/L = L : Inputs start pulse.
Selects driver voltage. This pin is internally pulled up to V
DD2
.
V
sel
= V
DD2
or OPEN: V
DD2
= 3.3 V
±
0.3 V, V
sel
= L: V
DD2
= 5.0 V
±
0.5 V
Inputs shift clock to shift register. Display data is loaded to data register at rising
edge of this pin.
Start pulse output goes high at rising edge of 80th clock after start pulse has been
input, and serves as start pulse to driver in next stage. 80th clock of driver in first
stage serves as start pulse of driver in next stage.
Contents of data register are latched at rising edge, transferred to D/A converter,
and output as analog voltage corresponding to display data. Contents of initial
shift register are cleared after STB has been input. One pulse of this signal is
input when
µ
PD16641 is started, and then device operates normally. For STB
input timing, refer to
Relations between STB, Start Pulse, and Blanking Period
in Switching Characteristic Waveform.
Inputs
γ
-corrected power from external source.
V
SS2
≤
V
10
≤
V
9
≤
V
8
≤
V
7
≤
V
6
≤
V
5
≤
V
4
≤
V
3
≤
V
2
≤
V
1
≤
V
0
≤
V
DD2
V
SS2
≤
V
0
≤
V
1
≤
V
2
≤
V
3
≤
V
4
≤
V
5
≤
V
6
≤
V
7
≤
V
8
≤
V
9
≤
V
10
≤
V
DD2
Maintain gray scale power supply during gray scale voltage output.
3.3 V
±
0.3 V
V
sel
= V
DD2
or OPEN : V
DD2
= 3.3 V
±
0.3 V
: V
DD2
= 5.0 V
±
0.5 V
V
sel
= L
Ground
Ground
Pin Name
Driver output
Display data input
Description
Output 64 gray scale analog voltages converted from digital signals.
Inputs 18-bit-wide display gray scale data (6 bits)
×
3 dots (RGB).
D
X0
: LSB, D
X5
: MSB
STHR
Right shift start pulse I/O
STHL
Left shift start pulse I/O
V
sel
Driver voltage selection
CLK
Shift clock input
STB
Latch input
V
0
to V
10
γ
-corrected power supply
V
DD1
V
DD2
Logic circuit power supply
Driver circuit power supply
V
SS1
V
SS2
Logic ground
Driver ground
Caution Be sure to turn on power in the order V
DD1
, logic input, V
DD2
, and gray scale power (V
0
to V
10
), and
turn off power in the reverse order, to prevent the
µ
PD16641 from being damaged by latchup. Be
sure to observe this power sequence even during a transition period.
4
µ
PD16641
4. RELATION BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
The 11 major points on the
γ
characteristic curve of the LCD panel are arbitrarily set by external power supplies V
0
through V
10
. If the display data is 00
H
or 3F
H
, gray scale voltage V
0
or V
10
is output. If the display data is in the range
01
H
to 3E
H
, the high-order 3 bits select an external powers pair V
n+1
, V
n
. The low-order 3 bits evenly divide the range
of V
n+1
to V
n
into eight segments by means of D/A conversion (however, the ranges from V
9
to V
8
and from V
2
to V
1
are divided into seven segments) to output a 64 gray scale voltage.
D
X5
(MSB)
D
X4
D
X3
D
X2
D
X1
D
X0
(LSB)
High-order 3 bits:
γ-corrected
power selected
(V
n+1
, V
n
)
Low-order 3 bits: 3bit D/A
(range V
n
to V
n+1
is divided into 7 or 8 segments)
D
X5
0
0
0
0
1
1
1
1
V
DD2
D
X4
0
0
1
1
0
0
1
1
D
X3
0
1
0
1
0
1
0
1
V
n+1
to V
n
V
1
to V
2
V
2
to V
3
V
3
to V
4
V
4
to V
5
V
5
to V
6
V
6
to V
7
V
7
to V
8
V
8
to V
9
V
n
1
2
3
4
5
6
7
8
000 001 010 011 100 101 110 111
D
X2
to D
X0
gray scale supply specified
by 00
H
7 segments
V
n+1
V
0
V
1
V
2
8 segments
V
3
8 segments
V
4
8 segments
V
5
V
6
V
7
8 segments
V
8
7 segments
V
9
8 segments
8 segments
V
SS2
V
10
0
7
F
17
1F
Input data (HEX)
27
2F
37
3F
gray scale supply specified
by 3F
H
5
PCB设计
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