DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD16650
120-/128-OUTPUT TFT-LCD GATE DRIVER
The
µ
PD16650 is a TFT-LCD gate driver. Provided with a level shift circuit at the logic input, this chip can output
a high gate scan voltage for a CMOS-level input. The
µ
PD16650 has an output change-over function for switching
from the 120-output mode to the 128-output mode, and vice versa, thereby supporting the VGA, SVGA, and XGA
panels. Its output enable function (OE) enables installing the driver on either side.
FEATURES
• Output with high dielectric strength (on/off range: V
DD
- V
EE1
= 40 V
MAX
.)
• Built-in shift direction change-over function
• Shiftable negative supply voltage (V
EE1
) level (shift range: |V
EE1
- V
EE2
| = 10 V)
• Two acceptable CMOS input levels (3.3 and 5 V)
• Output enable function
• MC-selectable output count (MC = high: 120-output mode)
(MC = low : 128-output mode)
• Slim TCP
ORDERING INFORMATION
Part number
Package
TCP (TAB package)
Standard TCP (OL pitch = 220
µ
m)
µ
PD16650N-×××
µ
PD16650N-×××
Remark
When ordering, the customer can specify the external form of the TCP. Call one of our sales representatives
for more information.
Document No. S11041EJ1V0DS00 (1st edition)
(Previous No. IP-3677)
Date Published December 1995 P
Printed in Japan
©
1995
µ
PD16650
BLOCK DIAGRAM
V
CHA
R/L
LS
φ
X
LS
STVR
LS
128-bit shift register
LS
STVL
MC
LS
OE
LS
V
EE1
X
1
X
2
X
127
X
128
Remark
LS (level shifter): Interfaces the 5 V CMOS level with the V
DD
-V
EE2
level.
2
µ
PD16650
PIN CONNECTION DIAGRAM (
µ
PD16650N-×××)
X
128
X
127
X
126
V
DD
V
CHA
V
EE2
STVL
OE
X
70
X
69
X
68
X
67
X
66
X
65
(Copper foil side)
X
64
X
63
X
62
X
61
X
60
X
59
These pins are ineffective in the
120-output mode.
φ
X
R/L
V
CC
MC
V
SS
STVR
V
EE2
V
EE1
X
3
X
2
X
1
Caution
The V
CHA
pin should be connected to the V
DD
or V
EE2
pin on the TCP. (This method eliminates
the necessity to provide the V
CHA
input pin on the TCP, resulting in a reduction in the number
of required input pins.)
3
µ
PD16650
PIN DESCRIPTION
Pin symbol
X
1
to X
128
Pin name
Driver output
Description of function
Output scan signals to drive the TFT-LCD gate electrodes. The output changes
when the shift clock
φ
X
rises. The amplitude of the driver output is V
DD
- V
EE1
.
See the timing charts shown later for details of how to switch between the 120-
output mode and 128-output mode.
MC
Output count change-over
input
Receives a signal that changes the number of outputs. For the 120-output
mode, this pin must be supplied with a high level (V
CC
). For the 128-output
mode, it must be supplied with a low level (V
SS
or V
EE2
).
V
CHA
Logic voltage change-over
input
STVR
STVL
Start pulse input/output
Must be supplied with the V
EE2
level when the logic supply voltage is 3.3 V, and
with the V
DD
level when the logic supply voltage is 5.0 V.
Receives an input to the internal shift register. The input data is loaded on the
shift register at the positive-going edge of the shift clock
φ
X
. The scan signals
are output from X
1
to X
128
. The input/output level is the CMOS level.
Outputs a start pulse to the next stage if a cascade connection is used. In the
120-output mode, the start pulse is output at the negative-going edge of the
120th shift clock
φ
X
pulse, and cleared at the negative-going edge of the 121st
pulse. In the 128-output mode, the start pulse is output at the negative-going
edge of the 128th shift clock
φ
X
pulse, and cleared at the negative-going edge
of the 129th pulse.
R/L
Shift direction change-over
input
R/L = high (for shift right): STVR
→
X
1
→
X
128
→
STVL
R/L = low (for shift left)
: STVL
→
X
128
→
X
1
→
STVR
φ
X
Shift clock input
Receives a shift clock pulse for the internal shift register. A shift occurs at the
positive-going edge of the shift clock pulse.
OE
Output enable input
When this pin is at a high level, the driver output is fixed at a low level. The
shift register is not cleared, however. The internal logic circuit operates even
when the pin is at a high level.
synchronized with the clock.
The signal supplied to this pin is not
V
DD
Driver positive supply volt-
age
Receives the supply voltage for both the logic circuit and driver.
V
CC
Reference voltage
5
±0.5
V/3.3
±0.3
V
Reference voltage for the LS1 and LS2 level shifters.
V
SS
V
EE1
Ground
Driver negative supply volt-
age
Must be connected to the system ground.
V
EE1
(for the driver)
V
EE2
Driver negative supply volt-
age
V
EE2
(for the logic circuit)
4
µ
PD16650
CAUTIONS FOR USE
1)
Power-on sequence
To prevent latch-up disruption, the power must be switched on in the order:
V
CC
→
V
EE1
→
V
EE2
→
V
DD
→
Logic input
When witching off, reverse the order. This order must be observed also during transition.
2)
Insertion of bypass capacitors
The internal logic circuit operates at a high voltage. To make V
IH
and V
IL
immune to noise, use capacitors of
0.1
µ
F or so between supply voltages as shown below.
V
DD
V
CC
0.1
µ
F
V
SS
0.1
µ
F
V
EE2
0.1
µ
F
3)
Negative voltage level shift
If it is necessary to shift the level of a negative supply voltage, shift the V
EE1
(driver supply voltage) level. The
shift should be limited to within: V
EE2
≤
V
EE1
≤
V
EE2
+ 10 V
Note that shifting the V
EE1
level results in the ON-state output resistance and output fall time ratings being
changed.
4)
Handling the V
EE1
and V
EE2
driver negative supply voltage pins
For applications in which a negative supply voltage level is not shifted, connect the V
EE1
pin (driver supply voltage)
to the V
EE2
pin (logic supply voltage) outside the TCP. Fix all unused input pins to the V
EE2
level.
5
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