DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD16654
150/154 OUTPUT TFT-LCD GATE DRIVE
The
µ
PD16654 is a TFT-LCD gate driver. Because this gate driver has a level shift circuit for logic input, it can
output a high gate scanning voltage in response to a CMOS-level input.
Moreover, it can also drive both the XGA/SXGA panel (154 outputs) and SVGA panel (150 outputs) by changing
the number of outputs over between 150 and 154.
FEATURES
• High breakdown voltage output (ON/OFF range: V
DD2
-V
EE2
= 40 V MAX.)
• 3.3 V CMOS level input
• Number of output select function (150/154 outputs)
ORDERING INFORMATION
Part Number
Package
TCP (TAB package)
µ
PD16654N-×××
The TCP’s external shape is customized. To order your TCP’s external shape, please contact an NEC salesperson.
Document No. S11647EJ1V0DS00 (1st edition)
Date Published May 1998 N CP(K)
Printed in Japan
©
1998
µ
PD16654
3. PIN FUNCTIONS
Pin Symbol
O
1
to O
154
Pin Name
Driver output pins
Description
Scan signal output pins that drive the gate electrode of a TFT-LCD.
The status of each output pin changes in synchronization with the rising edge
of shift clock CLK. The output voltage of the driver is V
DD2
to V
EE2
.
Input/output pin of the internal shift register.
Start pulse signal is read at the rising edge of shift clock CLK and a scan
signal is output from the driver output pin. The interface of this terminal is
CMOS of 3.3 V.
When O
sel
signal is Low level, start pulse goes up to high level at the 154th
falling edge of shift clock CLK and goes down to low level at the 155th falling
edge.
And when O
sel
signal is High level, start pulse goes up to high level at the
150th falling edge of shift clock CLK and goes down to low level at the 151st
falling edge. The output level is V
CC
-V
SS
(logic level).
Shift clock input for the internal shift register. The contents of internal shift
register is shifted at the rising edge of CLK.
Shift direction switching input pin of the internal shift register.
R/L = H (right shift) : STVR
→
O
1
→
O
2
··· O
153
→
O
154
→
STVL
R/L = L (left shift) STVL
→
O
154
→
O
153
··· O
2
→
O
1
→
STVR
This pin fixes the driver output to the L level when it is high. However, the
shift register is not cleared. And, output enable actuation is asynchronous in
the clock. And, refer to “RELATIONS OF ENABLE INPUT AND OUTPUT
TERMINAL“.
Selects the number of outputs.
O
sel
= L : 154 outputs (SVGA)
O
sel
= H: 150 outputs (VGA, XGA, SXGA)
When O
sel
= H (150 outputs), O
76
through O
79
outputs of the shift register are
fixed to the V
EE2
level. Fix this pin to V
CC
(V
DD2
) or V
SS
(V
EE1
) on TCP.
Shared with internal logic and driver
3.3 V
±
0.3 V. Reference power supply for level shifter: LS
Connect this pin to the system ground.
Negative power supply for internal logic
STVR
STVL
Start pulse input/output pin
CLK
Shift clock input
R/L
Shift direction switching
input
O
E1
O
E2
O
E3
Enable input
O
sel
Number of output select
input
V
DD2
Positive power supply for
driver
Reference power supply
Ground (GND)
Negative power supply for
internal logic
Negative power supply for
driver
V
CC
V
SS
V
EE1
V
EE2
Negative power supply for driver
Caution 1. Power ON/OFF sequence
To prevent the
µ
PD16654 from damage due to latch up, turn on power in the order V
CC
→
V
EE1
,
V
EE2
and V
DD2
→
logic input. Turn off power in the reverse order. Observe these power
sequences even during transition period.
4
µ
PD16654
Caution 2. Inserting bypass capacitor
Because the internal logic operates at a high voltage (V
DD2
-V
EE1
), insert a bypass capacitor of
about 0.1
µ
F between the respective power pins as shown below to secure the noise margin
of V
IH
and V
IL
.
V
DD2
V
CC
0.1
µ
F
V
SS
0.1
µ
F
V
EE2
V
EE1
0.1
µ
F
0.1
µ
F
Do not input a switching signal to the O
sel
pin that selects the number of outputs. Connect this pin to V
CC
or V
SS
(V
EE1
).
5
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