DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD16662
240 OUTPUT LCD COLUMN (SEGMENT) DRIVER WITH BUILT-IN RAM
The
µ
PD16662 is a column (segment) driver which contains a RAM capable of full dot LCD drive.
With 240 outputs, this driver has a display RAM of 240 x 160 x 2 bits built in, and 4 gray scales of display are
possible. Any 4 gray scales can be selected from 25 levels of the gray scale pallet. The driver can be combined
with the
µ
PD16667 to display from 240 x 160 dots to 480 x 320 dots.
Features
•
Display RAM incorporated: 240 x 160 x 2 bits
•
Logic voltage: 3.0V to 3.6V
•
Duty: 1/160
•
Output count: 240 outputs
•
Capable of gray scale display: 4 gray scales (can be selected from 25 levels of the gray scale pallet)
•
Memory management: packed pixel system
•
8/16-bit data base
Ordering Information
Part number
Package
TCP(TAB)
Standard TCP (OLB: 0.2 mm pitch; folding)
µ
PD16662N -×××
•
µ
PD16662N - 051
The TCP’s external shape is custom-ordered. Therefore, if you have a shape in mind, please contact an NEC
salesperson.
The information in this document is subject to change without notice.
Document No. S12738EJ3V0DS00 (3rd edition)
Date Published November 1998 NS CP (K)
Printed in Japan
The mark
•
shows major revised points.
©
1998
µ
PD16662
Pin name
Classification
CPU I/F
Voltage
3.3 V
Pin Name
D0 to D15
A0 to A16
/CS
/OE
/WE
/UBE
RDY
Control signals
3.3 V
PL0
PL1
DIR
Note
I/O
I/O
I
I
I
I
I
O
I
I
I
Data bus 16
Address bus 17
Chip select
Read signal
Write signal
High byte enable
Function
Ready signal to CPU (Ready state at H)
Specifies the LSI allocation locations (No. 0 to 3).
Specifies the LSI allocation locations (No. 0 to 3).
Specifies the liquid-crystal panel allocation direction
(longitudinal; lateral)
MS
BMODE
/REFRH
TEST
/RESET
/DOFF
OSC1
OSC2
5.0 V
STB
I
I
I/O
I
I
I
-
-
I/O
Master/slave switching (Master mode at H)
Data bus bit select pin ("H" = 8bit, "L" = 16bit)
Self diagnostic reset pin (Wired OR connection)
Test pin (Test mode at H, using the pull-down buffer)
Reset
Display OFF signal input
Oscillator pin
Oscillator pin
Column driving signal strobe
(MS signal "H" = output, MS signal "L" = input )
/FRM
PULSE
L1
L2
/DOUT
Liquid-crystal drive
Powers
Y1 to Y240
GND
V
CC1
V
CC2
V
0
V
1
V
2
I/O
I/O
I/O
I/O
O
O
-
-
-
-
-
-
Frame signal(MS pin "H" = output , MS pin "L" = input )
25-gray level pulse modulation clock
Row driver drive level selection signal (1st line)
Row driver drive level selection signal (2nd line)
Display OFF signal output
Liquid-crystal drive output
Ground (two 5-V pins; three 3-V pins)
5-V power level
3.3-V power level
Liquid-crystal drive analog power
Liquid-crystal drive analog power
Liquid-crystal drive analog power
Remark
/xxx indicates active low signal.
Note
3.3-V power pins : D0 - D15, A0 - A16, /CS, /OE, /WE, /UBE, RDY, BMODE, PL0, PL1, DIR, OSC1,
OSC2, /RESET, /DOFF, TEST, MS
5-V power pins
: STB, /FRM, L1, L2, /DOUT, PULSE
2
µ
PD16662
Block Diagram
DIR
PL0, PL1
TEST
Address
input
control
Address
management
control
Arbiter
RAM
240 x 160 x 2 bit
A0 - A16
Control
/CS, /OE,
/WE, /UBE
RDY
BMODE
D0 - D15
Data bus
control
/REFRH
/RESET
MS
STOP
OSC1
CR
oscillator
OSC2
/DOFF
Liquid crystal
timing generation
3.3 V operation
PULSE /FRM STB
Data latch (1)
Gray scale
generation
circuit
Data latch (2)
Internal timing
generation
Gray level control
Self-diagnosis
circuit
Level shifter
3.3 V operation
5.0 V operation
DEC
5.0 V operation
Liquid crystal drive circuit
240 outputs
V0
V1
V2
PULSE
/FRM
STB /DOUT L1
L2
Y1 Y2 Y3
Y240
3
µ
PD16662
Block Functions
(1) Address management circuit
The address management circuit converts addresses transferred from the system through A0 to A16 into addresses
compatible with the memory map of the built-in RAM. This function can be used to address up to 480 x 320 dots with
four of these LSIs, thus making it possible to configure a liquid crystal display system without difficulty. Moreover,
addresses 1FFF0H to 1FFFFH are allocated to the gray scale pallet register, making it possible to choose any 4 gray
scales from the 25-level pallet.
(2) Arbiter
The arbiter adjusts the contention between the RAM access from the system and the RAM read on the liquid-crystal
drive side.
(3) RAM
Static RAM (single port) of 240 by 160 by 2 bits
(4) Data bus control
This circuit controls the data transfer directions through the read/write from the system. It also performs an 8/16-bit
switch via the BMODE pin.
(5) Gray scale generation circuit
This circuit realizes the 25 levels by frame thinning out and pulse width modulation.
(6) Internal timing generation
Internal timing to each block is generated from /FRM and STB signals.
(7) CR oscillator
The CR oscillator generates the clock which will become a criterion of the frame frequency in master mode. 1/2592
of this oscillation becomes the frame frequency. For example, if the frame frequency is 70 Hz, the required oscillation
frequency is 181.44 kHz. As the CR oscillator has a built-in capacitor, adjust the required oscillation frequency with
an external resistor.
In slave mode, the oscillation is stopped.
(8) Liquid crystal timing generation
In master mode, /FRM (frame signal), STB (column drive signal strobe), and PULSE (25-gray-scale pallet pulse
modulation clock) are generated.
(9) Gray scale control
This circuit realizes a four-gray scale display.
(10) Data latch (1)
Reads and latches 240-pixel data from the RAM.
(11) Data latch (2)
Latches 240-pixel data synchronously with the STB signal.
4
µ
PD16662
(12) Level shifter
The level shifter converts from the operating voltage (3.3 V) of the internal circuit to the liquid-crystal drive circuit
and low driver interface voltage (5 V).
(13) DEC
Decodes the gray scale display data to make it compatible with the liquid-crystal drive voltages V
0
, V
1
and V
2
.
(14) Liquid crystal drive circuit
This circuit selects one of the liquid-crystal drive powers V
0
, V
1
, and V
2
, which are compatible with the gray scale
display data and the display OFF signal (/DOFF), to generate the liquid crystal applied voltage.
(15) Self diagnostic circuit
If the operation timing of the master chip and slave chip has deviated due to external noise, this circuit will detect
the problem and generate a total column/driver refresh signal.
Address map image diagram (Example of VGA-half size configuration)
Column direction specified with A7 to A0
Y1
L1
Address progress direction
Row direction
specified with
A16 to A8
No.0
No.2
Y240 Y1
Y240
L160
L1
Address progress direction
No.1
Y240
Y1 Y240
No.3
Y1
L160
5
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