DATA SHEET
MOS INTEGRATED CIRCUITS
µ
PD16663
240-OUTPUT LCD COLUMN (SEGMENT) DRIVER WITH BUILT-IN RAM
DESCRIPTION
The
µ
PD16663 is a column (segment) driver device with built-in RAM. It is capable of driving a full-dot LCD.
There are 240 outputs that, with the 240
×
160
×
4-bit built-in display RAM, enable a 16-gray scale display. The
sixteen gray scales can be selected arbitrarily from a 49-stage palette. When combined with the
µ
PD16667, this
device can drive displays of 240
×
160 to 480
×
320 dots.
FEATURES
• Built-in display RAM: 240
×
160
×
4 bits
• Logic voltage: 3.0 to 3.6 V
• Duty cycle: 1/160
• Number of outputs: 240
• Gray scales: 16 (selectable from a palette of 49)
• Memory management: Packed pixel
• Compatible with 8-bit/16-bit data buses
ORDERING INFORMATION
Part number
Package
TCP (TAB)
2-side standard TCP
µ
PD16663N-×××
5
µ
PD16663N-051
Remark
The TCP's external shape is customized. To order the required shape, please contact
an NEC salesperson.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
Date Published
Printed in Japan
S13392EJ1V0DS00 (1st edition)
December 1999 NS CP(K)
The mark
5
shows major revised points.
©
1998, 1999
µ
PD16663
BLOCK DIAGRAM
DIR
PL0, PL1
TEST
Address
input control
Address
management
circuit
A
0
- A
16
Control
/CS, /OE,
/WE, /UBE
RDY
BMODE
D
0
- D
15
Arbiter
RAM
240 x 160 x 4 bits
/REFRH
/RESET
MS
STOP
OSC1
CR
oscillator
Data bus
control
Data latch (1)
Gray scale
generation
circuit
Data latch (2)
OSC2
/DOFF
LCD timing
generator
3.3-V operation
PULSE /FRM STB
Internal timing
generator
Gray scale control
Self-diagnostic
circuit
Level shifter
3.3-V operation
5.0-V operation
DEC
5.0-V operation
240 outputs of LCD
driver circuit
V
0
V
1
V
2
PULSE
/FRM
STB
/DOUT
L1
L2
Y
1
Y
2
Y
3
Y
240
Remark
/××× indicates active low signal.
2
Data Sheet S13392EJ1V0DS00
µ
PD16663
1. PIN FUNCTIONS
Classification
CPU Interface
Pin name
D
0
to D
15
A
0
to A
1
6
/CS
3.3 V
/OE
/WE
/UBE
RDY
Control signals
PL0
PL1
DIR
MS
BMODE
3.3 V
/REFRH
TEST
/RESET
/DOFF
OSC1
OSC2
STB
/FRM
5.0 V
PULSE
L1
L2
/DOUT
LCD drive
Power supply
Y
1
to Y
240
GND
V
CC1
V
CC2
V
0
V
1
V
2
Note
I/O
I/O
I
I
I
I
I
O
I
I
I
I
I
I/O
I
I
I
-
-
I/O
I/O
I/O
I/O
I/O
O
O
-
-
-
-
-
-
Data bus : 16 bits
Address bus : 17 bits
Chip select
Read signal
Write signal
Upper byte enable
Function
Ready signal issued to CPU ("H" sets ready status)
Specifies the LSI placement position (No. 0 to 3)
Specifies the LSI placement position (No. 0 to 3)
Specifies the direction of the LCD panel placement
Selects between master/slave ("H" sets master mode)
Selects the data bus bit ("H" sets 8 bits, "L" sets 16 bits)
Self-diagnostics reset pin (Wired-OR connection)
Test pin ("H" sets test mode, pull-down resistor is built-in)
Reset signal
Display OFF input signal
For external resistor for oscillator
For external resistor for oscillator
Column driving signal (MS pin "H" sets output, MS pin "L" sets input)
Frame signal (MS pin "H" sets output, MS pin "L" sets input)
25-gray-scale pulse modulation clock
Row driver driving level select signal (line 1)
Row driver driving level select signal (line 2)
Display OFF output signal
LCD drive output
Ground (× 2 for 5 V,
×
3 for 3.3 V)
5-V power supply
3.3-V power supply
LCD drive analog power supply
LCD drive analog power supply
LCD drive analog power supply
Note
3.3-V pins : D
0
to D
15
, A
0
to A
16
, /CS, /OE, /WE, /UBE, RDY, BMODE, PL0, PL1, DIR, OSC1, OSC2, /RESET,
/DOFF, TEST, MS
5-V pins
:STB, /FRM, L1, L2, /DOUT, PULSE
Remark
N.C. = Non-connection
Data Sheet S13392EJ1V0DS00
3
µ
PD16663
2. BLOCK FUNCTION
(1) Address management circuit
Converts an address transferred from the system via A
0
to A
16
to an address that corresponds to the on-
chip RAM memory map.
This function enables address management for a display size of up to 480 x 320 dots using four
µ
PD16663
LSIs, thus facilitating the configuration of LCD systems.
The allocation of addresses 1FFF80H to 1FFFEH (even addresses only) to the gray scale palette register
also allows the user to select any 16 gray scales from a palette of 49.
(2) Arbiter
Resolves a conflict between a RAM access from the system and a RAM read on the LCD drive side.
(3) RAM
240 x 160 x 4 bits of static RAM (single port).
(4) Data bus control
Controls the direction in which data is transferred according to whether the system is reading or writing.
The bus width can also be switched between 8 and 16 bits with the BMODE pin.
(5) Gray scale generation circuit
Culls frames and modulates the pulse width to realize 49 gray scales.
(6) Internal timing generator
Generates the internal timing for each block from the /FRM and STB signals.
(7) CR oscillator
In master mode, this oscillator generates the clock referenced for the frame frequency. The frame frequency
is determined by dividing this clock by 2592. To obtain a frame frequency of 70 Hz, therefore, an oscillation
frequency of 181.44 kHz is required. Because the CR oscillator is on chip, adjust the oscillation frequency
using an external resistor.
Oscillation is stopped in slave mode.
(8) LCD timing generator
In master mode, this generator generates /FRM (the frame signal), STB (the column driver signal strobe),
and PULSE (the 49-gray-scale pulse modulation clock).
(9) Gray scale control
This is a circuit for realizing a 16-gray-scale display.
4
Data Sheet S13392EJ1V0DS00
µ
PD16663
(10) Data latch (1)
Latches 240-pixel data read from RAM.
(11) Data latch (2)
Latches 240-pixel data in synchronization with the STB signal.
(12) Level shifter
Converts the internal circuit operating voltage (3.3 V) to the voltage required by the LCD driver and row
driver interface (5 V).
(13) DEC
Decodes the gray scale display data into the corresponding LCD drive voltages V
0
, V
1
, and V
2
.
(14) LCD driver circuit
Creates the voltage to be applied to the LCD by selecting one of LCD drive power supplies V
0
, V
1
, or V
2
,
according to the gray scale data and display off signal (/DOFF).
(15) Self-diagnostic circuit
Automatically detects any mismatch between the operation timings of the master and slave chips cause by
noise, etc., and issues a refresh signal to all the column drivers.
•
Address Map Image (Half VGA Size)
Column direction specified with A
7
to A
0
Y
1
Y
240
L1
Line direction specified
with A
16
to A
8
L160
L1
Address increases in this direction
L160
Y
240
No. 1
Y
1
Y
240
No. 3
Y
1
Address increases in this direction
No. 0
No. 2
Y
1
Y
240
Data Sheet S13392EJ1V0DS00
5
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