DATA SHEET
MOS INTEGRATED CIRCUIT
P
PD16666A
240-OUTPUT LCD ROW DRIVER
DESCRIPTION
The
P
PD16666A is a row (common) driver which contains a RAM capable of full-dot LCD display. With 240
outputs, this driver can be combined with a column (segment) driver
P
PD16661A which contains a RAM to display
VGA (640 by 480 dots), 1/2 VGA, or 1/4 VGA, etc. By combining it with the
P
PD16661A, the
P
PD16666A can provide
four gray levels by frame rate control.
With its built-in display RAM in the column driver, the driver kit can reduce current consumption, thus making it
most suitable for the display section of a PDA or portable terminal.
FEATURES
•
•
•
•
•
LCD-driven voltage: 20 to 36 V
Duty: 1/240
Driving type: 2 lines selected simultaneously
Output count: 240 outputs
Capable of gray level display: 4 gray levels (frame rate control)
ORDERING INFORMATION
Part No.
Package
TCP (TAB)
Standard TCP (OLB: 0.2 mm pitch; folding)
P
PD16666AN-XXX
P
PD16666AN-051
The TCP’s external shape is custom-ordered. Therefore, if you have a shape in mind, please contact an NEC
salesperson.
Document No. S12370EJ2V0DS00 (2nd edition)
Date Published October 1997 N
Printed in Japan
©
1997
P
PD16666A
BLOCK DIAGRAM
X
1
to X
240
V
DD
Liquid-crystal drive circuit
V1
V
EE
Selection control circuit
Q
1
to Q
120
Bidirectional shift register
DIR
V
CC1
V
SS
Level shifter
L1
L2
DOFFB’
STB
FRMB
½
Column driver interface
BLOCK FUNCTION
1. Liquid-crystal drive circuit
This circuit selects and outputs the level for liquid-crystal driving.
One of V
DD
, V
EE
, and V1 is selected by the output of the selection control circuit.
2. Selection control circuit
This circuit creates the signal which will select the level of the output signal, based on the output of the shift
register circuit and the driving level power selection signals L1 and L2
3. Bidirectional shift register circuit
This refers to the 120-bit bidirectional shift register circuit. The DIR signal can be used to switch over the shift
direction.
The data that has been entered from the FRMB terminal is shifted by the row drive signal strobe (STB).
4. Level shifter circuit
This circuit transforms the 5-V signals to the high-voltage signals for liquid-crystal driving.
2
P
PD16666A
PIN FUNCTIONS
Classification
Power
Pin Name
V
CC1
V
SS
V
DD
V
EE
V1
STB
FRMB
DOFFB’
L1
L2
DIR
I
I
I
I
I
I
Input/Output
Pad No.
Function
5 V power for level shifter
GND power for level shifter
Power for logic; liquid-crystal drive level power
Power for logic; liquid-crystal drive level power (GND)
Liquid-crystal drive level power
Row drive strobe signal
Frame signal
Display OFF signal
Drive level power selection signal (1st line)
Drive level power selection signal (2nd line)
Shift direction selection signal: when L (DIR = V
EE
), X
1
o
X
240
when H (DIR = V
DD
), X
240
o
X
1
Liquid-crystal drive output
Selects and outputs one of V
DD
, V
EE
, and V1.
Liquid-crystal
display timing
Liquid-crystal
drive output
X
1
to X
240
O
DETAILS OF PIN FUNCTIONS
•
STB (input)
Refers to the input pin of the row drive strobe signal.
The bidirectional shift register is shifted at STB’s rising edge.
•
FRMB (input)
Refers to the input pin of the frame signal.
The shift register data is read at STB’s rising edge.
•
DIR (input)
Refers to the input pin of the drive output’s shift direction selection signal.
When the shift direction selection signal (DIR) is “L”, the shift data (selection signal) is shifted from the drive
output X
1
to the X
240
direction. When “H”, it is shifted from the X
240
to the X
1
direction.
•
DOFFB’ (input)
Refers to the input pin of the display OFF signal.
It is placed in the display OFF status (all outputs at V1) at the “L” level. In the mean time, it reads the frame signal
and returns to the normal display status at the “H” level.
•
L1 & L2 (input)
Refer to the input pins of the drive level power selection signal.
In the case of the liquid-crystal drive output, the two lines are selected simultaneously by the shift register. L1
selects the first line, and L2 the second line. Both lines select V
DD
at “H”, and V
EE
at “L”.
3
P
PD16666A
POWER SUPPLY SEQUENCE OF CHIP SET
It is recommended to apply power in the following sequence.
V
CC2
o
V
CC1
o
input
o
V
DD
, V
EE
o
V0, V1, V2
Be sure to apply LCD drive voltages V0, V1, and V2 last.
ON
V
CC2
OFF
ON
V
CC1
OFF
4.5 V
Input
(A0-A16, CSB, OEB,
WEB, UBEB, D0-D15,
DOFFB)
0 s or
more
0V
3.3 V
3.3 V
RESETB
0V
0.3 V
CC2
100 ns or
more
V
Note
DD
0 s or
more
ON
OFF
OFF
V
EE
Note
ON
0 ns
or
more
ON
V0
OFF
ON
V1
OFF
ON
V2
OFF
Note
V
DD
and V
EE
do not need to be turned ON at the same time.
Caution
Turn off power to the chip set in the reverse sequence to the power application sequence.
4
P
PD16666A
EXAMPLE OF CONNECTING INTERNAL SCHOTTKY BARRIER DIODE OF MODULE TO
REINFORCE POWER SUPPLY PROTECTION
(Use a Schottky barrier diode with Vf = 0.5 V or less.)
V
DD
V
CC1
V2
V1
V0
V
SS
V
EE
Connect the diodes enclosed in the dotted line when V
0
is not 0 V (GND)
5
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