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MK2742-05STRLF

产品描述Video Clock Generator, 40.5MHz, CMOS, PDSO16, 0.150 INCH, SOIC-16
产品类别嵌入式处理器和控制器    微控制器和处理器   
文件大小44KB,共4页
制造商IDT (Integrated Device Technology)
标准
下载文档 详细参数 全文预览

MK2742-05STRLF概述

Video Clock Generator, 40.5MHz, CMOS, PDSO16, 0.150 INCH, SOIC-16

MK2742-05STRLF规格参数

参数名称属性值
是否Rohs认证符合
零件包装代码SOIC
包装说明0.150 INCH, SOIC-16
针数16
Reach Compliance Codecompli
ECCN代码EAR99
JESD-30 代码R-PDSO-G16
JESD-609代码e3
长度9.9695 mm
端子数量16
最高工作温度70 °C
最低工作温度
最大输出时钟频率40.5 MHz
封装主体材料PLASTIC/EPOXY
封装代码SOP
封装形状RECTANGULAR
封装形式SMALL OUTLINE
峰值回流温度(摄氏度)NOT SPECIFIED
主时钟/晶体标称频率27 MHz
认证状态Not Qualified
座面最大高度1.778 mm
最大供电电压5.5 V
最小供电电压4.5 V
标称供电电压5 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子面层MATTE TIN
端子形式GULL WING
端子节距1.27 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度3.937 mm
uPs/uCs/外围集成电路类型CLOCK GENERATOR, VIDEO
Base Number Matches1

文档预览

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ICRO
C
LOCK
Description
The MK2742 is a low cost, low jitter, high
performance clock synthesizer for MPEG I,
MPEG II, and set-top box based applications.
Using analog Phase-Locked Loop (PLL)
techniques, the device accepts a 27.00MHz crystal
or clock input to produce multiple output clocks
including the processor clock, 27MHz, 13.5MHz,
3.6864MHz, and a selectable audio clock. The
audio clocks (on the -03 and -04) and the
13.5MHz, 27MHz and 3.68MHz clocks are
exactly frequency locked to the 27.00MHz input
with zero ppm error, allowing audio and video to
track exactly.
MicroClock manufactures the largest variety of
Set-Top Box and multimedia clock synthesizers
for all applications. Consult MicroClock to
eliminate crystals and oscillators from your board.
MK2742
MPEG/Set-Top Clock Source
Features
• Packaged in 16 pin narrow (150 mil) SOIC
• Pin compatible upgrade to MK2741 with:
- zero ppm audio clock error (-03, -04)
- new processor frequencies
- support for low cost codecs (-05,-06)
• Selectable audio sampling frequencies support
32 kHz, 44.1 kHz, and 48 kHz in most DACs
• 27.00 MHz crystal or clock input
• Selectable processor frequencies
• Fixed clocks of 13.5, 27, and 3.6864 MHz
• Zero ppm error in 13.5, 27, and 3.686 MHz clocks
• 25mA output drive capability at TTL levels
• Advanced, low power, sub-micron CMOS process
• 5V±10% operating voltage
Block Diagram
VDD
GND
2
2
3
2
Output
Buffer
AS1:0
PS2:0
27.00 MHz
clock or
crystal
X1
Audio Clock
Processor Clock
3.6864 MHz
Clock Synthesis
and Control
Circuitry
Output
Buffer
Output
Buffer
Output
Buffer
X2
Clock
Buffer/
Crystal
Oscillator
13.5 MHz
÷2
Output
Buffer
27.00 MHz
1
Revision 10277
Printed 10/27/97
MicroClock Division of ICS•1271 Parkmoor Ave.•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax
MDS2742D

 
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