DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD16700
256-OUTPUT TFT-LCD GATE DRIVER
DESCRIPTION
The
µ
PD16700 is a TFT-LCD gate driver equipped with 256-output lines. It can output a high-gate scanning
voltage in response to CMOS level input because it provided with a level-shift circuit inside the IC circuit. It can also
drive the XGA/SXGA panel.
FEATURES
•
CMOS level input (3.3 V)
•
256 outputs
•
High-output voltage (V
DD2
-V
EE2
= amplitude: 40 V MAX.)
•
Capable of All-on outputting (AO)
ORDERING INFORMATION
Part Number
Package
TCP (TAB package)
µ
PD16700N-xxx
Remark
The TCP’s external shape is customized. To order the required shape, please contact an one of our sales
representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14085EJ1V1DS00 (1st edition)
Date Published July 2000 NS CP (K)
Printed in Japan
The mark
•
shows major revised points.
©
1999
µ
PD16700
3. PIN FUNCTIONS
Pin Symbol
O
1
to O
256
Pin Name
Driver output
Description
These pins output scan signals that drive the vertical direction (gate lines) of a TFT-LCD.
The output signals change in synchronization with the rising edge of shift clock CLK. The
driver output amplitude is V
DD2
- V
EE2
.
R,/L
STVR,
STVL
Shift direction select R,/L = H (right shift) : STVR
→
O
1
→
O
256
→
STVL
input
R,/L = L (left shift) : STVL
→
O
256
→
O
1
→
STVR
Start pulse
input/output
This is the input of the internal shift register. The start pulse is read at the rising edge of shift
clock CLK, and scan signals are output from the driver output pins. The input level is a
CMOS (3.3 V) level. The start pulse is output at the falling edge of the 256th clock of shigt
clock CLK, and is cleared at the falling edge of the 257th clock. The output level is V
DD1
-
V
SS
(logic level).
This pin inputs a shift clock to the internal shift register.
The shift operation is performed in synchronization with the rising edge of this input.
When this pin goes H, the driver output is fixed to V
EE2
level.
The shift register is not cleared.
OE
1
: O
1
, O
4
, ... O
250
, O
253
, O
256
OE
1
: O
2
, O
5
, ... O
251
, O
254
OE
1
: O
3
, O
6
, ... O
252
, O
255
When this pin goes L, the driver output is fixed to V
DD2
level. The shift register is not cleared.
This pin has priority over OE
1
to OE
3
.
3.3 V
±
0.3 V
CLK
OE
1
,OE
2
,OE
3
Shift clock input
Output enable input
•
AO
V
DD1
V
DD2
V
SS
V
EE1
All-on control
Logic power supply
Driver positive power 15 to 25 V
supply
The driver output : H level
Logic ground
Negative Power
supply for internal
operation
Driver negative
power supply
Connect this pin to the ground of the system.
–15 to –5 V
V
EE2
The driver output : L level (V
EE2
-V
EE1
< 6.0 V)
Cautions 1. To prevent latch up, turn on power to V
DD1
, V
EE1/2
, V
DD2
, and logic input in this order. Turn off
power in the reverse order. These power up/down sequence must be observed also during
transition period.
2. Insert a capacitor of about 0.1
µ
F between each power line, as shown below, to secure noise
margin such as V
IH
and V
IL
.
V
DD2
V
DD1
0.1
µ
F
V
SS
0.1
µ
F
V
EE1/2
0.1
µ
F
4
Data Sheet S14085EJ1V1DS00
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