DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD16715A
384-OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 64-GRAY SCALES)
DESCRIPTION
The
µ
PD16715A is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scales. Data input is
based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors
by output of 64 values
γ-corrected
by an internal D/A converter and 5-by-2 external power modules. Because the
output dynamic range is as large as V
SS2
+ 0.1 V to V
DD2
– 0.1 V, level inversion operation of the LCD’s common
electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion when mounted on a single side,
this source driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins
respectively output gray scale voltages of differing polarity. Assuring a maximum clock frequency of 55 MHz when
driving at 3.0 V, this driver is applicable to XGA/SXGA-standard TFT-LCD panels.
FEATURES
• CMOS level input
• 384 outputs
• Input of 6 bits (gradation data) by 6 dots
• Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter
Logic power supply (V
DD1
): 3.3 V
±
0.3 V
+
2.5
• Driver power supply (V
DD2
): 11.0 V –
2.0
V
• High-speed data transfer: f
CLK
= 55 MHz (internal data transfer speed when operating at 3.0 V)
•
• Output dynamic range V
SS2
+ 0.1 V to V
DD2
– 0.1 V
• Apply for only dot-line inversion
• Single bank arrangement is possible (POL)
• Display data inversion function (POL2)
•
Low power control function (LPC)
Single-sided mounting (Slim TCP)
•
•
ORDERING INFORMATION
Part Number
Package
TCP (TAB package)
µ
PD16715AN- xxx
Remark
The TCP’s external shape is customized. To order your TCP’s external shape, please contact an
NEC salesperson.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S13944EJ2V0DS00 (2nd edition)
Date Published December 1999 NS CP(K)
Printed in Japan
The mark
•
shows major revised points.
©
1998,1999
µ
PD16715A
1. BLOCK DIAGRAM
STHR
R,/L
CLK
STB
C
1
C
2
64-bit bidirectional shift register
STHL
V
DD1
V
SS1
C
63
C
64
D
00
to D
05
D
10
to D
15
D
20
to D
25
D
30
to D
35
D
40
to D
45
D
50
to D
55
POL2
Data register
POL
Latch
V
DD2
Level shifter
V
SS2
V
0
to V
9
D/A converter
Voltage follower output
LPC
S
1
S
2
S
3
S
384
Remark
/xxx indicates active low signal.
2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER
S
1
S
2
S
383
S
384
V
4
V
5
V
9
·····
V
0
Multi-
plexer
5
6-bit D/A converter
5
·····
POL
2
Data Sheet S13944EJ2V0DS00
µ
PD16715A
3. PIN CONFIGURATION (
µ
PD16715AN-×××
×××)
×××
V
SS2
V
DD2
R,/L
POL
STB
D
55
D
54
D
53
D
52
D
51
D
50
D
45
D
44
D
43
D
42
D
41
D
40
D
35
D
34
D
33
D
32
D
31
D
30
STHL
V
9
V
8
V
7
V
6
V
5
V
4
V
3
V
2
V
1
V
0
V
DD1
CLK
V
SS1
POL2
STHR
D
25
D
24
D
23
D
22
D
21
D
20
D
15
D
14
D
13
D
12
D
11
D
10
D
05
D
04
D
03
D
02
D
01
D
00
LPC
TEST
V
DD2
V
SS2
S
384
S
383
S
382
S
381
Copper Foil
Surface
S
4
S
3
S
2
S
1
Remark
This figure does not specify the TCP package.
Data Sheet S13944EJ2V0DS00
3
µ
PD16715A
4. PIN FUNCTIONS
(1/2)
Pin Symbol
S
1
to S
384
D
00
to D
05
D
10
to D
15
D
20
to D
25
D
30
to D
35
D
40
to D
45
D
50
to D
55
R,/L
Shift direction control
input
These refer to the start pulse input/output pins when driver ICs are connected in
cascade. The shift directions of the shift registers are as follows.
R,/L = H: STHR input, S
1
→
S
384
, STHL output
R,/L = L : STHL input, S
384
→
S
1
, STHR output
R,/L = H: Becomes the start pulse input pin.
R,/L = L : Becomes the start pulse output pin.
R,/L = H: Becomes the start pulse output pin.
R,/L = L : Becomes the start pulse input pin.
Refers to the shift register’s shift clock input. The display data is incorporated into
the data register at the rising edge. At the rising edge of the 64th clock after the
start pulse input, the start pulse output reaches the high level, thus becoming the
start pulse of the next-level driver. The initial-level driver’s 64th clock becomes
valid as the next-level driver’s start pulse is input. If 66 clock pulses are input after
input of the start pulse, input of display data is halted automatically. The contents
of the shift register are cleared at the STB’s rising edge.
The contents of the data register are transferred to the latch circuit at the rising
edge. And, at the falling edge, the gray scale voltage is supplied to the driver. It is
necessary to ensure input of one pulse per horizontal period.
POL = L: The S
2n–1
output uses V
0
to V
4
as the reference supply ;
The S
2n
output uses V
5
to V
9
as the reference supply.
POL = H : The S
2n–1
output uses V
5
to V
9
as the reference supply ;
The S
2n
output uses V
0
to V
4
as the reference supply.
S
2n-1
indicates the odd output: and S
2n
indicates the even output. Input of the POL
signal is allowed the setup time (t
POL
-
STB
) with respect to STB’s rising edge.
POL2
LPC
Data inversion
Driver voltage selection
POL2 = H : Display data is inverted.
POL2 = L : Display data is not inverted
The output buffer constant current source is blocked, reducing current consumption.
Low power mode (LPC = ‘H’: DC-level input possible). The condition that low power
mode can be used is that the load constant is at least 10 kΩ + 50 pF.
V
0
to V
9
γ
-corrected power
supplies
Input the
γ
-corrected power supplies from outside by using operational amplifier.
Make sure to maintain the following relationships. During the gray scale voltage
output, be sure to keep the gray scale level power supply at a constant level.
V
DD2
– 0.1 V > V
0
> V
1
> V
2
> V
3
> V
4
> V
5
> V
6
> V
7
> V
8
> V
9
> V
SS2
+ 0.1 V
Test pin. Please input H or Open.
3.3 V
±
0.3 V
11.0 V
+ 2.5
−
2.0
Pin Name
Driver output
Display data input
Description
The D/A converted 64-gray scale analog voltage is output.
The display data is input with a width of 36 bits, viz., the gray scale data (6 bits)
by 6 dots (2 pixels).
D
X0
: LSB, D
X5
: MSB
STHR
Right shift start pulse
input/output
Left shift start pulse
input/output
Shift clock input
STHL
CLK
STB
Latch input
POL
Polarity input
TEST
V
DD1
V
DD2
V
SS1
V
SS2
Test pin
Logic power supply
Driver power supply
Logic ground
Driver ground
V
Grounding
Grounding
4
Data Sheet S13944EJ2V0DS00
µ
PD16715A
Cautions 1. The power start sequence must be V
DD1
, logic input, and V
DD2
& V
0
to V
9
in that order. Reverse
this sequence to shut down. (Simultaneous power application to V
DD2
and V
0
to V
9
is possible.)
2. To stabilize the supply voltage, please be sure to insert a 0.47
µ
F bypass capacitor between
V
DD1
-V
SS1
and V
DD2
-V
SS2
. Furthermore, for increased precision of the D/A converter, insertion of a
bypass capacitor of about 0.01
µ
F is also advised between the
γ
-corrected power supply
terminals (V
0
, V
1
, V
2
, ···, V
9
) and V
SS2
.
5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
The
µ
PD16715A incorporates a 6-bit D/A converter whose odd output pins and even output pins output respectively
gray scale voltages of differing polarity with respect to the LCD's counter electrode (common electrode) voltage. The
D/A converter consists of ladder resistors and switches. The ladder resistors r
0
to r
62
are so designed that the ratios
between the LCD panel's
γ
- corrected voltages and V
0'
to V
63'
and V
0"
to V
63"
are roughly equal; and their respective
resistance values are as shown on next page. Among the 5-by-2
γ
-corrected voltages, input gray scale voltages of
the same polarity with respect to the common voltage, for the respective five
γ
-corrected voltages of V
0
to V
4
and V
5
to V
9
Figure 5-1 shows the relationship between the driving voltages such as liquid-crystal driving voltages V
DD2
and V
SS2
,
common electrode potential V
COM
, and
γ
- corrected voltages V
0
to V
9
and the input data. Be sure to maintain the
voltage relationships of
V
DD2
– 0.1 V > V
0
> V
1
> V
2
> V
3
> V
4
> V
5
> V
6
> V
7
> V
8
> V
9
> V
SS2
+ 0.1 V.
Figures 5-2 and 5-3 show the relationship between the input data and the output voltage. Therefore, please do not
use it for
γ
- corrected power supply level inversion in double-sided mounting.
Figure 5−1. Relationship Between Input Data and
γ
- corrected Power Supply
−
V
DD2
0.1 V
V
0
8
V
1
24
V
2
24
V
3
7
V
4
V
COM
V
5
7
V
6
24
V
7
Split interval
24
V
8
8
V
9
0.1 V
V
SS2
00
08
20
38
3F
Input Data (HEX)
Data Sheet S13944EJ2V0DS00
5
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