DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD16750
384-OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 256-GRAY SCALES)
DESCRIPTION
The
µ
PD16750 is a source driver for TFT-LCDs capable of dealing with displays with 256-gray scales. Data input is
based on digital input configured as 8 bits by 6 dots (2 pixels), which can realize a full-color display of 16,777,216
colors by output of 256 values
γ
-corrected by an internal D/A converter and 8-by-2 external power modules.
Because the output dynamic range is as large as V
DD2
−
0.2 V to V
SS2
+ 0.2 V, level inversion operation of the LCD’s
common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and
column line inversion when mounted on a single side, this source driver is equipped with a built-in 8-bit D/A converter
circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity.
Assuring a maximum clock frequency of 40 MHz when driving at 3.0 V, this driver is applicable to XGA-standard TFT-
LCD panels and SXGA TFT-LCD panels. This driver is applicable to SXGA TFT-LCD panels by input display signal 2
systems (Clock divide).
FEATURES
•
CMOS level input
•
384 outputs
•
Input of 8 bits (gradation data) by 6 dots
•
Capable of outputting 256 values by means of 8-by-2 external power modules (16 units) and a D/A converter
•
Output dynamic range: V
DD2
– 0.2 V to V
SS2
+ 0.2 V
•
High-speed data transfer: f
CLK
= 40 MHz (internal data transfer speed when operating at 3.0 V)
•
Apply for dot-line inversion, n-line inversion and column line inversion
•
Output voltage polarity inversion function (POL)
•
Display data inversion function (POL21/22)
•
Logic power supply voltage (V
DD1
) : 3.3 V
±
0.3 V
•
Driver power supply voltage (V
DD2
) : 9.0 V
±
0.5 V
•
Low power control function (LPC)
ORDERING INFORMATION
Part Number
Package
TCP (TAB package)
µ
PD16750N-xxx
Remark
The TCP’s external shape is customized. To order the required shape, please contact one of our sales
representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S13719EJ4V0DS00 (4th edition)
Date Published April 2000 NS CP (K)
Printed in Japan
The mark
•
shows major revised points.
©
1998
µ
PD16750
1. BLOCK DIAGRAM
STHR
R,/L
CLK
STB
C
1
C
2
STHL
V
DD1
V
SS1
C
63
C
64
64-bit bidirectional shift register
D
00
- D
07
D
10
- D
17
D
20
- D
27
D
30
- D
37
D
40
- D
47
D
50
- D
57
POL21
POL22
Data register
POL
Latch
V
DD2
Level shifter
V
SS2
V
0
- V
15
D/A converter
Voltage follower output
LPC
S
1
S
2
S
3
S
384
Remark
/xxx indicates active low signal.
2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER
S
1
S
2
S
383
S
384
V
7
V
8
V
15
·····
V
0
Multi-
plexer
8
8-bit D/A converter
8
·····
POL
2
Data Sheet S13719EJ4V0DS00
µ
PD16750
3. PIN CONFIGURATION (
µ
PD16750N-xxx)
•
•
V
SS2
V
DD2
V
14
V
12
V
10
V
8
V
6
V
4
V
2
V
0
R,/L
D
50
D
51
D
52
D
53
D
54
D
55
D
56
D
57
D
40
D
41
D
42
D
43
D
44
D
45
D
46
D
47
D
30
D
31
D
32
D
33
D
34
D
35
D
36
D
37
POL21
POL22
POL
STB
STHL
V
DD1
CLK
V
SS1
LPC
STHR
D
20
D
21
D
22
D
23
D
24
D
25
D
26
D
27
D
10
D
11
D
12
D
13
D
14
D
15
D
16
D
17
D
00
D
01
D
02
D
03
D
04
D
05
D
06
D
07
V
1
V
3
V
5
V
7
V
9
V
11
V
13
V
15
V
DD2
V
SS2
S
384
S
383
S
382
Copper Foil
Surface
S
3
S
2
S
1
Remark
This figure does not specify the TCP package.
Data Sheet S13719EJ4V0DS00
3
µ
PD16750
4. PIN FUNCTIONS
Pin Symbol
S
1
to S
384
D
00
to D
07
D
10
to D
17
D
20
to D
27
D
30
to D
37
D
40
to D
47
D
50
to D
57
R,/L
Shift direction control These refer to the start pulse input/output pins when driver ICs are connected in cascade.
input
The shift directions of the shift registers are as follows.
R,/L = H
R,/L = L
STHR
Right shift start pulse R,/L = H
input/output
STHL
Left shift start pulse
input/output
CLK
Shift clock input
R,/L = L
R,/L = H
R,/L = L
: STHR input, S
1
→
S
384
, STHL output
: STHL input, S
384
→
S
1
, STHR output
: Becomes the start pulse input pin.
: Becomes the start pulse output pin.
: Becomes the start pulse output pin.
: Becomes the start pulse input pin.
Pin Name
Driver output
Display data input
Description
The D/A converted 256-gray-scale analog voltage is output.
The display data is input with a width of 48 bits, viz., the gray scale data (8 bits) by 6 dots (2
pixels).
D
X0
: LSB, D
X7
: MSB
Refers to the shift register’s shift clock input. The display data is incorporated into the data
register at the rising edge of the 64th clock after the start pulse input, the start pulse output
reaches the high level, thus becoming the start pulse of the next-level driver.
STB
Latch input
The contents of the data register are transferred to the latch circuit at the rising edge. And,
at the falling edge, the gray scale voltage is supplied to the driver. It is necessary to ensure
input of one pulse per horizontal period.
POL
Polarity input
POL = L
: The S
2n–1
output uses V
0
to V
7
as the reference supply. The S
2n
output uses V
8
to V
15
as the reference supply.
POL = H : The S
2n–1
output uses V
8
to V
15
as the reference supply. The S
2n
output uses V
0
to V
7
as the reference supply.
S
2n-1
indicates the odd output: and S
2n
indicates the even output. Input of the POL signal is
allowed the setup time(t
POL
-
STB
) with respect to STB’s rising edge.
POL21
POL22
Data inversion
Data inversion can invert when display data is loaded.
POL21/22 = H : Data inversion loads display data after inverting it.
POL21/22 = L : Data inversion does not invert input data.
POL21: D
00
to D
07
, D
10
to D
17
, D
20
to D
27
POL22: D
30
to D
37
, D
40
to D
47
, D
50
to D
57
LPC
Low power control
input
The output buffer constant current source is blocked, reducing current consumption. In lower
power mode (LPC = L: DC-level input possible), the ordinary static current consumption can
be reduced by approx. 33 %.
V
0
to V
15
Input the
γ
-corrected power supplies from outside by using operational amplifier. Make sure
to maintain the following relationships. During the gray scale voltage output, be sure to keep
the gray scale level power supply at a constant level.
V
DD2
−
0.2 V > V
0
> V
1
> V
2
> V
3
> V
4
> V
5
> V
6
> V
7
> 0.5 V
DD2
0.5 V
DD2
−
0.3 V > V
8
> V
9
> V
10
> V
11
> V
12
> V
13
> V
14
> V
15
> V
SS2
+ 0.2 V
V
DD1
V
DD2
V
SS1
V
SS2
Logic power supply
Driver power supply
Logic ground
Driver ground
3.3 V
±
0.3 V
9.0 V
±
0.5 V
Grounding
Grounding
Data Sheet S13719EJ4V0DS00
γ
-corrected power
supplies
4
µ
PD16750
Cautions 1. The power start sequence must be V
DD1
, logic input, and V
DD2
& V
0
to V
15
in that order.
Reverse this sequence to shut down (Simultaneous power application to V
DD2
and V
0
to V
15
is
possible.).
2. To stabilize the supply voltage, please be sure to insert a 0.1-
µ
F bypass capacitor between
V
DD1
-V
SS1
and V
DD2
-V
SS2
. Furthermore, for increased precision of the D/A converter, insertion
of a bypass capacitor of about 0.01
µ
F is also advised between the
γ
-corrected power supply
terminals (V
0
, V
1
, V
2
,....., V
15
) and V
SS2
.
Data Sheet S13719EJ4V0DS00
5
51单片机
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