HV5522/HV5530
HV5622/HV5630
32-Channel Serial To Parallel Converter
With Open Drain Outputs
Ordering Information
Package Options
Device
HV5522
HV5530
HV5622
HV5630
Recommended
Operating V
PP
max
220V
300V
220V
300V
44 J-Lead Quad
Ceramic Chip Carrier
HV5522DJ
HV5530DJ
HV5622DJ
HV5630DJ
44 J-Lead Quad
Plastic Chip Carrier
HV5522PJ
HV5530PJ
HV5622PJ
HV5630PJ
44 Lead Quad
Plastic Gullwing
HV5522PG
HV5530PG
HV5622PG
HV5630PG
Die
HV5522X
HV5530X
HV5622X
HV5630X
Features
s
Processed with HVCMOS
®
technology
s
Sink current minimum 100mA
s
Shift register speed 8MHz
s
Polarity and Blanking inputs
s
CMOS compatible inputs
s
Forward and reverse shifting options
s
Diode to V
PP
allows efficient power recovery
s
44-lead ceramic surface mount package
s
Hi-Rel processing available
General Description
The HV55 and HV56 are low-voltage serial to high-voltage
parallel converters with open drain outputs. These devices have
been designed for use as drivers for AC-electroluminescent
displays. They can also be used in any application requiring
multiple output high voltage current sinking capabilities such as
driving inkjet and electrostatic print heads, plasma panels, vacuum
fluorescent, or large matrix LCD displays.
These devices consist of a 32-bit shift register, 32 latches, and
control logic to perform the polarity select and blanking of the
outputs. Data is shifted through the shift register on the high to low
transition of the clock. The HV55 shifts in the counterclockwise
direction when viewed from the top of the package, and the HV56
shifts in the clockwise direction. A data output buffer is provided
for cascading devices. This output reflects the current status of
the last bit of the shift register. Operation of the shift register is not
affected by the LE (latch enable), BL (blanking), or the POL
(polarity) inputs. Transfer of data from the shift register to the latch
occurs when the LE (latch enable) input is high. The data in the
latch is stored when LE is low.
Absolute Maximum Ratings
Supply voltage, V
DD1
Output voltage, V
PP1
Logic input levels
1
Ground current
2
Continuous total power dissipation
3
Ceramic
Plastic
Operating temperature range
Storage temperature range
Lead temperature 1.6mm (1/16 inch)
from case for 10 seconds
HV5530/HV5630
HV5522/HV5622
-0.5V to +15V
-0.5V to +315V
-0.5V to +230V
-0.5V to V
DD
+ 0.5V
1.5A
1500mW
1200mW
Ceramic -55°C to +125°C
Plastic -40°C to +85°C
-65°C to +150°C
260°C
Notes:
1. All voltages are referenced to V
SS
.
2. Duty cycle is limited by the total power dissipated in the package.
3. For operation above 25°C ambient derate linearly to maximum operating
temperature at 20°C for plastic and at 15mW/°C for ceramic.
12-73
HV5522/HV5530/HV5622/HV5630
Electrical Characteristics
(over recommended operating conditions unless noted)
DC Characteristics
Symbol
I
DD
I
DDQ
I
O(OFF)
I
IH
I
IL
V
OH
V
OL
V
OC
Parameter
V
DD
supply current
Quiescent V
DD
supply current
Off state output current
High-level logic input current
Low-level logic input current
High-level output data out
Low-level output voltage
HV
OUT
clamp voltage
HV
OUT
Data out
V
DD
- 1.0V
15.0
1.0
-1.5
Min
Max
15
100
10
1
-1
Units
mA
µA
µA
µA
µA
V
V
V
V
Conditions
f
CLK
= 8MHz
F
DATA
= 4MHz
V
IN
= 0V
All outputs high
All SWS parallel
V
IH
= V
DD
V
IL
= 0V
I
Dout
= -100µA
I
HVout
= +100mA
I
Dout
= +100µA
I
OL
= -100mA
AC Characteristics
(V
DD
= 12V, T
C
= 25°C)
Symbol
f
CLK
t
W
t
SU
t
H
t
ON
t
DHL
t
DLH
t
DLE
t
WLE
t
SLE
Clock frequency
Clock width high or low
Data set-up time before clock falls
Data hold time after clock falls
Turn on time, HV
OUT
from enable
Delay time clock to data high to low
Delay time clock to data low to high
Delay time clock to LE low to high
Width of LE pulse
LE set-up time before clock falls
50
50
50
62
25
10
500
100
100
Parameter
Min
Max
8
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
R
L
= 2KΩ to V
PP
MAX
C
L
= 15pF
C
L
= 15pF
Conditions
Recommended Operating Conditions
Symbol
V
DD
HV
OUT
V
IH
V
IL
f
CLK
T
A
Logic supply voltage
High voltage output
HV5530 and HV5630
HV5522 and HV5622
High-level input voltage
Low-level input voltage
Clock frequency
Operating free-air temperature
Plastic
Ceramic
-40
-55
Parameter
Min
10.8
-0.3
-0.3
V
DD
- 2V
0
Max
13.2
+300
+220
V
DD
2.0
8
+85
+125
Units
V
V
V
V
V
MHz
°C
°C
12-74
HV5522/HV5530/HV5622/HV5630
Functional Block Diagram
Polarity
Blanking
Latch Enable
HV
OUT
1
Data Input
Clock
Latch
32-Bit
Shift
Register
Latch
HV
OUT
2
(Outputs 3 to 30
not shown)
HV
OUT
31
Latch
HV
OUT
32
Data Out
Latch
Function Table
Inputs
Function
All on
All off
Invert mode
Load S/R
Load
Latches
Transparent
Latch mode
Data
X
X
X
H or L
X
X
L
H
CLK
X
X
X
↓
LE
X
X
L
L
↑
↑
BL
L
L
H
H
H
H
H
H
POL
L
H
L
H
H
L
H
H
Shift Reg
1 2…32
*
*
*
*…*
*…*
*…*
Outputs
HV Outputs
1
2…32
On
Off
*
*
*
*
Off
On
On…On
Off…Off
*…*
*…*
*…*
*…*
*…*
*…*
Data Out
*
*
*
*
*
*
*
*
*
H or L *…*
*
*
L
H
*…*
*…*
*…*
*…*
H or L
H or L
↓
↓
H
H
Notes:
H = high level, L = low level, X = irrelevant,
↓
= high-to-low transition,
↑
= low-to-high transistion.
* = dependent on previous stage’s state before the last CLK
↓
or last LE high.
12-76
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