Supertex inc.
32-Channel Serial to Parallel Converter
With Open Drain Outputs
Features
►
►
►
►
HV5522
General Description
►
Processed with HVCMOS
®
technology
►
Sink current minimum 100mA
Shift register speed 8.0MHz
Polarity and Blanking inputs
CMOS compatible inputs
Forward and reverse shifting options
The HV5522 is a low-voltage serial to high-voltage parallel converter
with open drain outputs. This device has been designed for use as a
driver for AC-electroluminescent displays. It can also be used in any
application requiring multiple output high voltage current sinking
capabilities such as driving inkjet and electrostatic print heads,
plasma panels, vacuum fluorescent, or large matrix LCD displays.
This device consists of a 32-bit shift register, 32 latches, and control
logic to perform the polarity select and blanking of the outputs. Data
is shifted through the shift register on the high to low transition of the
clock. The HV5522 shifts in the counter clockwise direction when
viewed from the top of the package. A data output buffer is provided
for cascading devices. This output reflects the current status of
the last bit of the shift register. Operation of the shift register is not
affected by the LE (latch enable), BL (blanking), or the POL (polarity)
inputs. Transfer of data from the shift register to the latch occurs
when the LE (latch enable) input is high. The data in the latch is
stored when LE is low.
►
Diode to VPP allows efficient
power recovery
Functional Block Diagram
POL
BL
LE
DATA
IN
CLK
HV
OUT
1
Latch
HV
OUT
2
Latch
32-Bit
Shift
Register
Latch
(Outputs 3 to 30 not shown)
HV
OUT
31
HV
OUT
32
DATA
OUT
Latch
Doc.# DSFP-HV5522
C072313
Supertex inc.
www.supertex.com
HV5522
Ordering Information
Part Number
HV5522PG-G
HV5522PG-G M919
HV5522PJ-G
HV5522PJ-G M903
Package
44-Lead PQFP
44-Lead PQFP
44-Lead PLCC
44-Lead PLCC
Packing
96/Tray
500/Reel
27/Tube
500/Reel
44
1
Pin Configuration
-G denotes a lead (Pb)-free / RoHS compliant package
Absolute Maximum Ratings
Parameter
Supply voltage, V
DD
1
Output voltage, V
PP
1
Logic input levels
1
Ground current
2
Continuous total power dissipation
3
Operating temperature range
Storage temperature range
-0.5V to +15V
-0.5V to +230V
-0.5V to V
DD
+0.5V
1.5A
1200mW
-40
O
C to +85
O
C
-65
O
C to +150
O
C
44-Lead PQFP
(top view)
1 44
6
40
44-Lead PLCC
(top view)
Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied. Continuous operation of the device
at the absolute rating level may affect device reliability. All voltages are referenced to device
ground.
Product Marking
Top Marking
YYW W
Notes:
1. All voltages are referenced to V
SS
2. Duty cycle is limited by the total power dissipated in the package
3. For operation above 25°C ambient derate linearly to maximum operating
temperature at 20mW/°C.
HV5522PG
LLLL LLLL L
Bottom Marking
CCCCCCCC
AAA
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
Recommended Operating Conditions
Sym
V
DD
V
IH
V
IL
f
CLK
T
A
Parameter
Logic voltage supply
Input high voltage
Input low voltage
Clock frequency
Operating free-air temperature
Min
10.8
-0.3
V
DD
-2.0
0
-
-40
Max
13.2
+220
V
DD
2.0
8.0
+85
Units
V
V
V
V
MHz
O
Package may or may not include the following marks: Si or
44-Lead PQFP
Top Marking
HV
OUT
High voltage output
YY = Year Sealed
WW = Week Sealed
HV5522PJ
LLLLLLLLLL
L = Lot Number
A = Assembler ID
Bottom Marking
C = Country of Origin*
= “Green” Packaging
YYWW AAA
CCCCCCCCCCC
C
*May be part of top marking
Package may or may not include the following marks: Si or
Power-Up Sequence
44-Lead PLCC
Power-up sequence should be the following:
1. Connect ground
2. Apply V
DD
3. Set all inputs to a known state
Power-down sequence should be the reverse of the above.
Typical Thermal Resistance
Package
44-Lead PQFP
44-Lead PLCC
θ
ja
51
O
C/W
37
O
C/W
Doc.# DSFP-HV5522
C072313
2
Supertex inc.
www.supertex.com
HV5522
Electrical Characteristics
(over recommended operating conditions unless otherwise noted)
DC Characteristics
Sym
I
DD
I
DDQ
I
O(OFF)
I
IH
I
IL
V
OH
V
OL
V
OC
Parameter
V
DD
supply current
V
DD
supply current (quiescent)
Off state output current
High-level logic input current
Low-level logic input current
High-level output data out
Low-level output voltage
HV
OUT
clamp voltage
(V
DD
= 12V, T
C
= 25
O
C)
Min
-
-
-
-
-
V
DD
-1.0V
HV
OUT
Data out
-
-
-
Max
15
100
10
1.0
-1.0
-
15
1.0
-1.5
Units
mA
µA
µA
µA
µA
V
V
V
V
Conditions
f
CLK
= 8.0MHz, F
DATA
= 4.0MHz
V
IN
= 0V
All outputs high, all SWS parallel
V
IH
= V
DD
V
IL
= 0V
I
DOUT
= -100µA
I
HVOUT
= +100mA
I
DOUT
= +100µA
I
OL
= -100mA
AC Characteristics
Sym
f
CLK
t
W
t
SU
t
H
t
ON
t
DHL
t
DLH
t
DLE
t
WLE
t
SLE
Parameter
Min
-
62
25
10
-
-
-
50
50
50
Max
8.0
-
-
-
500
100
100
-
-
-
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
---
---
---
---
R
L
= 2.0KΩ to V
PP
max.
C
L
= 15pF
C
L
= 15pF
---
---
---
Clock frequency
Clock width, high or low
Data set-up time before CLK falls
Data hold time after CLK falls
Turn-on time, HV
OUT
from enable
Delay time clock to data high to low
Delay time clock to data low to high
Delay time clock to LE low to high
Width of LE pulse
LE setup time before clock falls
Input and Output Equivalent Circuits
VDD
VDD
HV
OUT
DATA
IN
DATA
OUT
HV
IN
VSS
VSS
VSS
Logic Inputs
Logic Data Output
High Voltage Outputs
Doc.# DSFP-HV5522
C072313
3
Supertex inc.
www.supertex.com
HV5522
Switching Waveforms
DATA
IN
V
IH
50%
t
SU
CLK
50%
t
WH
50%
t
WL
50%
DATA
OUT
t
DLH
50%
t
DHL
50%
t
DLE
HV
OUT
w/ S/R HIGH
t
ON
t
WLE
50%
t
SLE
V
OH
10%
V
OL
Data Valid
t
H
50%
50%
50%
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
V
IH
V
IL
LE
Functional Table
Inputs
Function
All on
All off
Invert mode
Load S/R
Load latches
Transparent latch
mode
Data
X
X
X
H or L
X
X
L
H
CLK
X
X
X
↓
H or L
H or L
↓
↓
LE
X
X
L
L
↑
↑
H
H
BL
L
L
H
H
H
H
H
H
POL
L
H
L
H
H
L
H
H
Shift Reg
1
*
*
*
H or L
*
*
L
H
2...32
*...*
*...*
*...*
*...*
*...*
*...*
*...*
*...*
Outputs
HV Outputs
1
On
Off
*
*
*
*
Off
On
2...32
On...On
Off...Off
*...*
*...*
*...*
*...*
*...*
*...*
Data Out
*
*
*
*
*
*
*
*
*
Notes:
H = high level, L = low level, X = irrelevant, ↓ = high-to-low transition, ↑ = low-to-high transistion.
* dependent on previous stage’s state before the last CLK ↓ or last LE high.
Doc.# DSFP-HV5522
C072313
4
Supertex inc.
www.supertex.com
HV5522
44-Lead PQFP Pin Description
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Doc.# DSFP-HV5522
C072313
Function
HV
OUT
11
HV
OUT
12
HV
OUT
13
HV
OUT
14
HV
OUT
15
HV
OUT
16
HV
OUT
17
HV
OUT
18
HV
OUT
19
HV
OUT
20
HV
OUT
21
HV
OUT
22
HV
OUT
23
HV
OUT
24
HV
OUT
25
HV
OUT
26
HV
OUT
27
HV
OUT
28
HV
OUT
29
HV
OUT
30
HV
OUT
31
HV
OUT
32
DATA OUT
N/C
N/C
N/C
POL
CLK
VSS
VDD
LE
DATA IN
BL
N/C
HV
OUT
1
HV
OUT
2
HV
OUT
3
HV
OUT
4
HV
OUT
5
HV
OUT
6
HV
OUT
7
HV
OUT
8
HV
OUT
9
HV
OUT
10
Description
High voltage outputs.
Data output pin.
No internal connection.
Inverts the polarity of the HV
OUT
pins
Clock pin, shift registers shifts data on falling edge of input clock.
Reference voltage, usually ground.
Logic supply voltage.
Latch enable pin, data is shifted from shift register to latches on logic input high.
Data input pin.
Blanking pin sets all HV
OUT
pins low or high depending upon state of polarity.
See function table.
No internal connection.
High voltage outputs.
5
Supertex inc.
www.supertex.com
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