IDTQS29FCT2052AT/BT/CT
HIGH-SPEED CMOS 8-BIT BUS INTERFACE REGISTER TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
HIGH-SPEED CMOS
IDTQS29FCT2052AT/BT/CT
8-BIT BUT INTERFACE
REGISTER TRANSCEIVER
FEATURES:
−
−
−
−
−
−
−
−
−
Pin and function compatible to the 29FCT2052 and
29FCT2052/53T
CMOS power levels: <7.5mW static
Undershoot clamp diodes on all inputs
True TTL input and output compatibility
Ground bounce controlled outputs
Reduced output swing of 0 to 3.5V
Built-in 25Ω series resistor outputs reduce reflection and other
system noise
A, B, and C speed grades with 5.8ns t
PD
for C speed guaranteed
with 50pF loads
Available in SOIC and QSOP packages
DESCRIPTION:
The QS29FCT2052T is an 8-bit, high-speed, CMOS TTL-compatible,
registered bus transceiver with 3-state outputs and a 25Ω resistor, useful
for driving transmission lines and reducing system noise. The QS29FCT2052
series part can replace the FCT52 series to reduce noise in an existing
design. All outputs have clamp diodes for undershoot noise suppression.
All outputs have ground bounce suppression. Outputs will not load an active
bus when Vcc is removed from the device.
FUNCTIONAL BLOCK DIAGRAM
A BUS
25
Ω
OEA
A
Register
CEB
CPB
B
Register
OEB
CEA
CPA
25
Ω
B BUS
INDUSTRIAL TEMPERATURE RANGE
1
c
2001 Integrated Device Technology, Inc.
FEBRUARY 2001
DSC-5394/-
IDTQS29FCT2052AT/BT/CT
HIGH-SPEED CMOS 8-BIT BUS INTERFACE REGISTER TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
(1)
Unit
V
°C
mA
mA
mA
FCTL
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Symbol
V
TERM
Description
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current Max Sink Current/Pin
Input Diode Current, V
IN
< 0
Output Diode Current, V
OUT
< 0
Max.
– 0.5 to +7
– 65 to +150
120
– 20
– 50
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
OEB
CPA
CEA
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
SO24-2 19
SO24-8
18
17
16
15
14
13
V
CC
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
OEA
CPB
CEB
T
STG
I
OUT
I
IK
I
OK
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
CAPACITANCE
(T
A
= +25
O
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
8
8
Max.
—
—
Unit
pF
pF
FCT_1
NOTE:
1. This parameter is measured at characterization but not tested.
SOIC/ QSOP
TOP VIEW
FUNCTION TABLES
Inputs
CPA
X
↑
X
Description
X
↑
CPB
X
X
↑
↑
X
CEA
H
L
H
L
L
(1)
Outputs
CEB
H
H
L
L
L
Ax
Hold
Load
Hold
X
Load
Bx
Hold
Hold
Load
Load
X
PIN DESCRIPTION
Name
Ax
Bx
CPA
CPB
CEA
CEB
OEA
OEB
I/O
I/O
I/O
I
I
I
I
I
I
A Bus
B Bus
Register A Clock Input
Register B Clock Input
Register A Clock Enable
Register B Clock Enable
Output Enable, Reg. B to Bus A
Output Enable, Reg. A to Bus B
Inputs
CPA
X
X
X
X
CPB
X
X
X
X
CEA
X
X
X
X
CEB
X
X
X
X
OEA
H
L
H
L
OEB
L
H
H
L
Ax
Z
Outputs
Bx
Reg. A
Z
Z
Reg. A
Reg. B
Z
Reg. B
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedence
↑
= LOW-to-HIGH Transition
2
IDTQS29FCT2052AT/BT/CT
HIGH-SPEED CMOS 8-BIT BUS INTERFACE REGISTER TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= -40°C to +85°C, V
CC
= 5.0V ± 5%
Symbol
V
IH
V
IL
∆V
T
I
IH
I
IL
I
OZ
I
OR
V
IC
V
OH
V
OL
R
OUT
Parameter
Input HIGH Level
Input LOW Level
Input Hysteresis
Input HIGH Current
Input LOW Current
Off-State Output Current (Hi-Z)
Current Drive
Input Clamp Voltage
Output HIGH Voltage
Output LOW Voltage
Output Resistance
V
CC
= Max.
V
CC
= Max., V
OUT
= 2.0V
(2)
V
CC
= Min., I
IN
= –18mA, T
A
= 25
°
C
(2)
V
CC
= Min.
V
CC
= Min.
V
CC
= Min.
I
OH
= -15mA
I
OL
= 12mA
I
OL
= 12mA
0
≤
V
IN
≤
Vcc
—
50
—
2.4
—
20
—
—
–0.7
—
—
28
±5
—
–1.2
—
0.5
40
µA
mA
V
V
V
Ω
Test Conditions
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
TLH
- V
THL
for all inputs
V
CC
= Max.
0
≤
V
IN
< Vcc
Min.
2
—
—
—
Typ.
(1)
—
—
0.2
—
Max.
—
0.8
—
±5
Unit
V
V
V
µA
NOTES:
1. Typical values are at V
CC
= 5.0V, T
A
= 25°C.
2. This parameter is guaranteed but not tested.
POWER SUPPLY CHARACTERISTICS
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= -40°C to +85°C, V
CC
= 5.0V ± 5%
Symbol
I
CC
Parameter
Quiescent Power Supply Current
Test Conditions
(1)
V
CC
= Max.
freq = 0
0V
≤
V
IN
≤
0.2V or
Vcc-0.2V
≤
V
IN
≤
Vcc
V
CC
= Max.
V
IN
= 3.4V
(2)
freq = 0
V
CC
= Max.
Outputs Open and Enabled
One Bit Toggling
50% Duty Cycle
Other inputs at GND or Vcc
(3,4)
Min.
—
Max.
1.5
Unit
mA
∆I
CC
Supply Current per Input TTL Inputs HIGH
—
2
mA
I
CCD
Supply Current per Input per MHz
—
0.25
mA/MHz
FCTL
NOTES:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
2. Per TLL driven input (V
IN
= 3.4V).
3. For flip-flops, I
CCD
is measured by switching one of the data input pins so that the output changes every clock cycle. This is a measurement of
device power consumption only and does not include power to drive load capacitance or tester capacitance.
4. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
3
IDTQS29FCT2052AT/BT/CT
HIGH-SPEED CMOS 8-BIT BUS INTERFACE REGISTER TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(1)
29FCT2052AT
Symbol
t
PHL
t
PLH
t
PZH
t
PZL
t
PHZ
t
PLZ
t
S
t
H
t
SCE
t
HCE
t
W
Parameter
Propagation
CP to Ax, Bx
Output Enable Time
(2)
OE
to Ax, Bx
Output Disable Time
(2,3)
OE
to Ax, Bx
Data Setup Time
Ax, Bx, to CP
Data Hold Time
Ax, Bx, to CP
Clock Enable Setup Time,
CE
to CP
Clock Enable Hold Time,
CE
to CP
Clock Pulse Width, HIGH or LOW
(3)
Delay
(2)
Min.
2
1.5
2
2
2
2
2
3
Max.
10
10.5
10
—
—
—
—
—
29FCT2052BT
Min.
2
1.5
2
2
1.5
2
2
3
Max.
6.5
7
5.5
—
—
—
—
—
29FCT2052CT
Min.
2
1.5
1.5
2
1.5
2
2
3
Max.
5.8
7
5.5
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. C
LOAD
= 50pF, R
LOAD
= 500Ω unless otherwise noted.
2. Minimums guaranteed but not tested.
3. This parameter is guaranteed by design but not tested.
4
IDTQS29FCT2052AT/BT/CT
HIGH-SPEED CMOS 8-BIT BUS INTERFACE REGISTER TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
500
Ω
V
IN
Pulse
Generator
D.U.T.
50pF
R
T
C
L
500
Ω
V
OUT
7.0V
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
All Other Tests
Open
FCTL
Switch
Closed
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
FC T L lin k
SET-UP, HOLD, AND RELEASE TIMES
DATA
INPUT
t
SU
TIM ING
INPUT
ASYNCHR ONOUS CONTROL
PRES ET
CLEA R
ETC.
SYNCHRO NOUS CONTROL
PRES ET
CLEA R
CLO CK ENABLE
ETC.
t
REM
t
H
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
FC T L lin k
PULSE WIDTH
LOW -HIGH-LO W
PULS E
t
W
HIGH-LO W -HIGH
PULS E
FC T L lin k
1.5V
1.5V
t
SU
t
H
PROPAGATION DELAY
SAM E PHASE
INPUT TRANSITIO N
t
PLH
OUTPUT
t
PLH
OPPO SITE PHASE
INPUT TRANSITIO N
t
PHL
t
PHL
3V
1.5V
0V
V
OH
1.5V
V
OL
3V
1.5V
0V
FC T L lin k
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
CONTROL
INPUT
t
PZL
OUTPUT
N OR MA LLY
LOW
SW ITCH
C LO SE D
t
PZH
OUTPUT
N OR MA LLY
HIGH
SW ITCH
OPEN
3.5V
1.5V
0.3V
t
PHZ
0.3V
1.5V
0V
0V
FC T L lin k
1.5V
t
PLZ
0V
3.5V
V
OL
V
OH
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
≤
10MHz; Zo
≤
50Ω; t
F
≤
2.5ns;
t
R
≤
2.5ns.
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
