TDA8034HN
Smart card interface
Rev. 3.1 — 5 September 2011
Product data sheet
1. General description
The TDA8034HN is a cost-effective analog interface for asynchronous and synchronous
smart cards operating at 5 V, 3 V or 1.8 V. Using few external components, the
TDA8034HN provides all supply, protection and control functions between a smart card
and the microcontroller.
2. Features and benefits
Integrated circuit smart card interface in an HVQFN24 package
5 V, 3 V or 1.8 V smart card supply
Very low power consumption in Deep Shutdown mode
Three protected half-duplex bidirectional buffered I/O lines (C4, C7 and C8)
V
CC
regulation:
5 V, 3 V or 1.8 V
5 % using two low ESR multilayer ceramic capacitors: one of
220 nF and one of 470 nF
current spikes of 40 nA/s (V
CC
= 5 V and 3 V) or 15 nA/s (V
CC
=1.8 V) up to
20 MHz, with controlled rise and fall times and filtered overload detection of
approximately 120 mA
Thermal and short-circuit protection for all card contacts
Automatic activation and deactivation sequences triggered by a short-circuit, card
take-off, overheating, falling V
DD
, V
DD(INTF)
or V
DDP
Enhanced card-side ElectroStatic Discharge (ESD) protection of > 6 kV
External clock input up to 26 MHz connected to pin XTAL1
Card clock generation up to 20 MHz using pins CLKDIV1 and CLKDIV2 with
synchronous frequency changes of f
xtal
,
1
2
f
xtal, 1
4
f
xtal
or
1
8
f
xtal
Non-inverted control of pin RST using pin RSTIN
Compatible with ISO 7816, NDS and EMV 4.2 payment systems
Supply supervisor for killing spikes during power on and off:
using a fixed threshold
using an external resistor bridge with threshold adjustment
Built-in debouncing on card presence contacts (typically 8 ms)
Multiplexed status signal using pin OFFN
NXP Semiconductors
TDA8034HN
Smart card interface
3. Applications
Pay TV
Electronic payment
Identification
Bank card readers
4. Quick reference data
Table 1.
Quick reference data
V
DDP
= 5 V; V
DD
= 3.3 V; V
DD(INTF)
= 3.3 V; f
xtal
= 10 MHz; GND = 0 V; T
amb
= 25 °C; unless otherwise specified.
Symbol
Supply
V
DDP
power supply voltage
pin V
DDP
; regulator input
V
CC
= 5 V
V
CC
= 3 V and 1.8 V
V
DD
V
DD(INTF)
I
DD
supply voltage
interface supply voltage
supply current
pin V
DD
pin V
DD(INTF)
shutdown mode
deep shutdown mode
active mode
I
DDP
power supply current
shutdown mode; f
xtal
stopped
active mode; f
CLK
=
1
2
f
xtal
;
no load
I
DD(INTF)
interface supply current
shutdown mode
active mode
Card supply voltage: pin V
CC[1]
V
CC
supply voltage
active mode; I
CC
< 65 mA DC
5 V card
3 V card
1.8 V card
active mode; current pulses of
40 nA/s at I
CC
< 200 mA;
t < 400 ns
5 V card
3 V card
active mode; current pulses of
15 nA/s at I
CC
< 200 mA,
t < 400 ns; 1.8 V card
V
ripple(p-p)
I
CC
General
t
deact
P
tot
T
amb
TDA8034HN
Parameter
Conditions
Min
Typ
Max
Unit
4.85
3
2.7
1.6
-
-
-
-
-
-
-
5
3.3
3.3
3.3
-
-
-
-
-
-
-
5.5
5.5
3.6
V
DD
+ 0.3
35
12
2
5
1.5
6
2
V
V
V
V
A
A
mA
A
mA
A
mA
4.75
2.85
1.71
5.0
3.05
1.83
5.25
3.15
1.89
V
V
V
4.65
2.76
1.66
5.0
-
-
5.25
3.20
1.94
V
V
V
peak-to-peak ripple voltage
supply current
deactivation time
total power dissipation
ambient temperature
from 20 kHz to 200 MHz
V
CC
= 0 V to 5 V, 3 V or 1.8 V
see
Figure 8 on page 11
T
amb
=
25 C
to +85
C
-
-
35
-
25
-
-
90
-
-
350
65
250
0.25
+85
mV
mA
s
W
C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1. — 5 September 2011
2 of 30
NXP Semiconductors
TDA8034HN
Smart card interface
[1]
To meet these specifications, V
CC
should be decoupled to pin GND using two ceramic multilayer capacitors of low ESR with values of
either 100 nF or one 220 nF and one 470 nF.
5. Ordering information
Table 2.
Ordering information
Package
Name
TDA8034HN/C1
HVQFN24
Description
plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 4
4
0.85 mm
Version
SOT616-1
Type number
6. Block diagram
10
μF
100 nF
100 nF
V
DD
17
V
DD(INTF)
SUPPLY
R1
(1)
GND
12
V
DDP
16
PORADJ 18
R2
INTERNAL
REFERENCE
VOLTAGE
SENSE
INTERNAL
OSCILLATOR
CLKUP
ALARMN
EN1
PVCC
V
CC
LDO
15 V
CC
470 nF
220 nF
PRESN
8
RSTIN
CMDVCCN
OFFN
CLKDIV1
CLKDIV2
VCC_SEL2
VCC_SEL1
I/OUC
3
5
19
6
7
2
4
20
CRYSTAL
OSCILLATOR
LEVEL
SHIFTER
CLOCK
CIRCUIT
SEQUENCER
EN4
RESET
GENERATOR
CLOCK
GENERATOR
14 RST
EN3
CLK
EN2
13 CLK
CARD
CONNECTOR
C5
C1
C2
C3
C4
THERMAL
PROTECTION
C6
I/O
TRANSCEIVER
I/O
TRANSCEIVER
I/O
TRANSCEIVER
9 I/O
C7
C8
TDA8034HN
AUX1UC
21
10 AUX1
11 AUX2
AUX2UC
22
1
100 nF
23
XTAL1
24
XTAL2
001aal136
V
DD(INTF)
ALARMN, CLKUP, EN1, PVCC, EN4, EN3, EN2 and CLK are internal signals.
(1) Optional external resistor bridge, if not required connect pin PORADJ to V
DD(INTF)
Fig 1.
TDA8034HN
Block diagram
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1. — 5 September 2011
3 of 30
NXP Semiconductors
TDA8034HN
Smart card interface
7. Pinning information
7.1 Pinning
22 AUX2UC
21 AUX1UC
24 XTAL2
23 XTAL1
20 I/OUC
terminal 1
index area
V
DD(INTF)
VCC_SEL2
RSTIN
VCC_SEL1
CMDVCCN
CLKDIV1
1
2
3
4
5
6
19 OFFN
18 PORADJ
17 V
DD
16 V
DDP
15 V
CC
14 RST
13 CLK
GND 12
001aal137
TDA8034HN
AUX1 10
CLKDIV2
Transparent top view
Fig 2.
Pin configuration
7.2 Pin description
Table 3.
Symbol
V
DD(INTF)
Pin description
Pin Supply
1
Type
[1]
Description
interface supply voltage
5 V or 3 V V
CC
voltage selection control signal:
active LOW: V
CC
= 3 V when pin VCC_SEL1 is HIGH
active HIGH: V
CC
= 5 V
RSTIN
3
V
DD(INTF)
I
V
DD(INTF)
I
microcontroller card reset input; active HIGH
1.8 V V
CC
voltage selection control signal:
active LOW: V
CC
= 1.8 V
active HIGH: disables 1.8 V selection
CMDVCCN 5
CLKDIV1
CLKDIV2
PRESN
I/O
AUX1
AUX2
GND
CLK
RST
V
CC
6
7
8
9
10
11
12
13
14
15
V
DD(INTF)
I
V
DD(INTF)
I
V
DD(INTF)
I
V
DD(INTF)
I
V
CC
V
CC
V
CC
-
V
CC
V
CC
V
CC
I/O
I/O
I/O
G
O
O
P
microcontroller start activation sequence input; active LOW
sets the clock frequency on pin CLK in association with pin CLKDIV2; see
Table 4
sets the clock frequency on pin CLK in association with pin CLKDIV1; see
Table 4
card presence contact input; active LOW
[2]
card input/output data line (C7)
[3]
auxiliary card input/output data line (C4)
[3]
auxiliary card input/output data line (C8)
[3]
ground
card clock (C3)
card reset (C2)
card supply (C1); decouple to pin GND using one 470 nF capacitor close to pin V
CC
and one 220 nF capacitor close to card socket contact C1 with an ESR < 100 m
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
V
DD(INTF)
P
V
DD(INTF)
I
VCC_SEL2 2
VCC_SEL1 4
TDA8034HN
Product data sheet
Rev. 3.1. — 5 September 2011
PRESN
AUX2 11
7
8
I/O
9
4 of 30
NXP Semiconductors
TDA8034HN
Smart card interface
Table 3.
Symbol
V
DDP
V
DD
PORADJ
OFFN
I/OUC
AUX1UC
AUX2UC
XTAL1
XTAL2
[1]
[2]
[3]
[4]
[5]
Pin description
…continued
Pin Supply
16
17
18
19
20
21
22
23
24
V
DDP
V
DD
Type
[1]
Description
P
P
low-dropout regulator input supply voltage
digital supply voltage
power-on reset threshold adjustment input using an optional external resistor bridge
NMOS interrupt to microcontroller
[4]
; active LOW; see
Section 8.10 on page 11
microcontroller input/output data line
[5]
auxiliary microcontroller input/output data line
[5]
auxiliary microcontroller input/output data line
[5]
crystal connection input
crystal connection output
V
DD(INTF)
I
V
DD(INTF)
O
V
DD(INTF)
I/O
V
DD(INTF)
I/O
V
DD(INTF)
I/O
V
DD
V
DD
I
O
I = input, O = output, I/O = input/output, G = ground and P = power supply.
If pin PRESN is LOW, the card is considered to be present. During card insertion, debouncing can occur on these signals. To counter
this, the TDA8034HN has a built-in debouncing timer (typically 8 ms).
Uses an internal 11 k pull-up resistor connected to pin V
CC
.
Uses an internal 20 k pull-up resistor connected to pin V
DD(INTF)
.
Uses an internal 10k pull-up resistor connected to pin V
DD(INTF)
8. Functional description
Remark:
Throughout this document the ISO 7816 terminology conventions have been
adhered to and it is assumed that the reader is familiar with these.
8.1 Power supplies
The power supply voltage ranges are as follows:
•
V
DDP
: 4.85 V to 5.5 V when VCC_SEL2 is HIGH (V
CC
= 5 V)
•
V
DDP
: 3 V to 5.5 V when VCC_SEL2 is LOW (V
CC
= 3 V) or when VCC_SEL1 is LOW
(V
CC
= 1.8 V)
•
V
DD
: 2.7 V to 3.6 V
All interface signals to the system controller are referenced to V
DD(INTF)
. All card contacts
remain inactive during power up or power down. After powering up the device, pin OFFN
remains LOW until pin CMDVCCN is set HIGH and pin PRESN is LOW. During power
down, pin OFFN goes LOW when V
DDP
falls below the falling threshold voltage (V
th
).
The internal oscillator frequency (f
osc(int)
) is only used during the activation sequences.
When the card is not activated (pin CMDVCCN is HIGH), the internal oscillator is in low
frequency mode to reduce power consumption.
This device has a Low Drop-Off (LDO) voltage regulator connected to pin V
CC
, and is
used instead of a DC-to-DC converter. It ensures a minimum V
CC
of 4.75 V and that the
power supply voltage on pin V
DDP
does not fall below 4.85 V when pin VCC_SEL2 is
HIGH, for a maximum load current of 65 mA.
TDA8034HN
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1. — 5 September 2011
5 of 30
模拟与混合信号
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
