A43L2616B
1M X 16 Bit X 4 Banks Synchronous DRAM
Document Title
1M X 16 Bit X 4 Banks Synchronous DRAM
Revision History
Rev. No.
0.0
0.1
0.2
1.0
1.1
1.2
1.3
History
Initial issue
Change I
CC1
to 70mA
Change I
CC6
to 1.5mA
Add 54B Pb-Free CSP package type
Final version release
Change BS0 to BA0, BS1 to BA1
Add p
art numbering scheme
Erase 54B CSP package type
Issue Date
August 24, 2006
February 14, 2007
March 15, 2007
April 3, 2007
August 15, 2007
February 15, 2008
December 16, 2009
Remark
Preliminary
Final
(December, 2009, Version 1.3)
AMIC Technology, Corp.
A43L2616B
1M X 16 Bit X 4 Banks Synchronous DRAM
Feature
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks / Pulse
RAS
MRS cycle with address key programs
- CAS Latency (2,3)
- Burst Length (1,2,4,8 & full page)
-
Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Clock Frequency: 166MHz @ CL=3
143MHz @ CL=3
Burst Read Single-bit Write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
Commercial Temperature Operation : 0
°
C~70
°
C
Industrial Temperature Operation : -40
°
C~85
°
C for –U
grade
Available in 54-pin TSOP(II) package
Package is available to lead free (-F series)
All Pb-free (Lead-free) products are RoHS compliant
General Description
The A43L2616B is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 X 1,048,576 words by
16 bits, fabricated with AMIC’s high performance CMOS
technology. Synchronous design allows precise cycle
control with the use of system clock.
I/O transactions are possible on every clock cycle. Range
of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high
bandwidth,
high
performance
memory
system
applications.
Pin Configuration
TSOP (II)
VDDQ
VSSQ
DQ
15
DQ
12
DQ
14
DQ
13
DQ
11
DQ
10
UDQM
VDDQ
VSSQ
CKE
VSS
VSS
DQ
8
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
A43L2616BV
1
VDD
2
DQ
0
3
VDDQ
4
DQ
1
5
DQ
2
6
VSSQ
7
DQ
3
8
DQ
4
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
VSSQ
A10/AP
VDDQ
VDD
LDQM
VDD
CS
BA0
BA1
A0
A1
WE
CAS
RAS
DQ
5
DQ
6
DQ
7
A2
A3
(December, 2009, Version 1.3)
1
AMIC Technology, Corp.
VSS
DQ
9
NC
CK
A11
NC
A9
A8
A7
A6
A5
A4
A43L2616B
Block Diagram
LWE
I/O Control
Data Input Register
Bank Select
DQM
Row Buffer
Refresh Counter
1M X 16
1M X 16
1M X 16
1M X 16
Row Decoder
Output Buffer
Sense AMP
CLK
Address Register
DQi
LCBR
LRAS
Column Buffer
ADD
Column Decoder
Latency & Burst Length
LRAS
LCAS
LRAS LCBR LWE
LWCBR
Timing Register
Programming Register
DQM
CLK
CKE
CS
RAS
CAS
WE
DQM
(December, 2009, Version 1.3)
2
AMIC Technology, Corp.
A43L2616B
Pin Descriptions
Symbol
Name
Description
CLK
CS
System Clock
Chip Select
Active on the positive going edge to sample all inputs.
Disables or Enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE
Clock Enable
CKE should be enabled at least one clock + tss prior to new command.
Disable input buffers for power down in standby.
Row / Column addresses are multiplexed on the same pins.
A0~A11
Address
Row address : RA0~RA11, Column address: CA0~CA7
Selects bank to be activated during row address latch time.
BA0, BA1
Bank Select Address
Selects band for read/write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column Address
Strobe
Write Enable
Data Input/Output
Mask
Data Input/Output
Power
Supply/Ground
Data Output
Power/Ground
No Connection
Latches column addresses on the positive going edge of the CLK with
CAS
low.
Enables column access.
Enables write operation and Row precharge.
Makes data output Hi-Z, t SHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power Supply: +3.3V
±
0.3V/Ground
Provide isolated Power/Ground to DQs for improved noise immunity.
WE
L(U)DQM
DQ
0-15
VDD/VSS
VDDQ/VSSQ
NC/RFU
(December, 2009, Version 1.3)
3
AMIC Technology, Corp.
A43L2616B
Absolute Maximum Ratings*
Voltage on any pin relative to VSS (Vin, Vout ) . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +4.6V
Voltage on VDD supply relative to VSS (VDD, VDDQ )
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to +4.6V
Storage Temperature (T
STG
) . . . . . . . . . . -55
°
C to +150
°
C
Soldering Temperature X Time (T
SOLDER
) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
°
C X 10sec
Power Dissipation (P
D
) . . . . . . . . . . . . . . . . . . . . . . . . .1W
Short Circuit Current (Ios) . . . . . . . . . . . . . . . . . . . . 50mA
*Comments
Permanent device damage may occur if “Absolute
Maximum Ratings” are exceeded.
Functional operation should be restricted to recommended
operating condition.
Exposure to higher than recommended voltage for extended
periods of time could affect device reliability.
Capacitance (T
A
=25°C, f=1MHz)
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Input Capacitance
CI1
CI2
A0 to A11, BA0, BA1
CLK, CKE,
CS
,
RAS
,
CAS
,
WE
,
DQM
DQ0 to DQ15
2.5
2.5
4
3.8
3.8
6.5
pF
pF
pF
Data Input/Output Capacitance
CI/O
DC Electrical Characteristics
Recommend operating conditions (Voltage referenced to VSS = 0V, T
A
= 0ºC to +70ºC or T
A
= -40ºC to +85ºC)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
Output Loading Condition
VDD,VDDQ
V
IH
V
IL
V
OH
V
OL
I
IL
I
OL
3.0
2.0
-0.3
2.4
-
-5
-5
3.3
3.0
0
-
-
-
-
3.6
VDD+0.3
0.8
-
0.4
5
5
V
V
V
V
V
μ
A
μ
A
Note 1
I
OH
= -2mA
I
OL
= 2mA
Note 2
Note 3
See Figure 1
Note:
1. V
IL
(min) = -1.5V AC (pulse width
≤
5ns).
2. Any input 0V
≤
VIN
≤
VDD + 0.3V, all other pins are not under test = 0V
3. Dout is disabled, 0V
≤
Vout
≤
VDD
(December, 2009, Version 1.3)
4
AMIC Technology, Corp.
微控制器 MCU
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