HT48E30
Preliminary
Features
·
Operating voltage:
·
HALT function and wake-up feature reduce power
8-Bit I/O Type MCU (With EEPROM)
f
SYS
=4MHz: 2.2V~5.5V
f
SYS
=8MHz: 3.3V~5.5V
·
Low voltage reset function
·
23 bidirectional I/O lines (max.)
·
1 interrupt input shared with an I/O line
·
8-bit programmable timer/event counter with overflow
consumption
·
4-level subroutine nesting
·
Up to 0.5ms instruction cycle with 8MHz system clock
at V
DD
=5V
·
Bit manipulation instruction
·
14-bit table read instruction
·
63 powerful instructions
·
10
6
erase/write cycles EEPROM data memory
·
EEPROM data retention > 10 years
·
All instructions in one or two machine cycles
·
In system programming (ISP)
·
24/28-pin SKDIP/SOP package
interrupt and 8-stage prescaler
·
On-chip crystal and RC oscillator
·
Watchdog Timer
·
2048´14 program memory ROM (MTP)
·
128´8 data memory EEPROM
·
96´8 data memory RAM
·
Buzzer driving pair and PFD supported
General Description
The HT48E30 is an 8-bit high performance, RISC archi-
tecture microcontroller device specifically designed for
multiple I/O control product applications.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, HALT and
wake-up functions, watchdog timer, buzzer driver, as
well as low cost, enhance the versatility of these devices
to suit a wide range of application possibilities such as
industrial control, consumer products, subsystem con-
trollers, etc.
Block Diagram
IN T /P G 0
In te rru p t
C ir c u it
S T A C K
4 L e v e ls
T M R 0
IN T C
T M R 0 C
P G 0
In s tr u c tio n
R e g is te r
M
U
X
W D T S
D A T A
M e m o ry
W D T P r e s c a le r
W D T
M
U
X
M
U
X
P r e s c a le r
T M R /P C 0
M
U
X
f
S
Y S
P ro g ra m
R O M
P ro g ra m
C o u n te r
E N /D IS
f
S
Y S
/4
M P
W D T O S C
P A C
In s tr u c tio n
D e c o d e r
A L U
T im in g
G e n e ra to r
S h ifte r
M U X
P A
B Z /B Z
P B C
P G 1
P G 2
P B
P C C
O S C 2
O S
R E
V D
V S
C 1
S
D
S
A C C
P C
P O R T C
P O R T B
P B 0 ~ P B 7
P O R T A
P A 0 ~ P A 7
S T A T U S
P C 0 ~ P C 5
D a ta M e m o ry
E E P R O M
E E C R
P G C
P G
P O R T G
P G 0
Rev. 0.00
1
January 12, 2004
Preliminary
Pin Assignment
P B 5
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
P B 4
P B 5
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
P B 4
P A 3
P A 2
P A 1
P A 0
P B 3
P B 2
P B 1 /B Z
P B 0 /B Z
V S S
P G 0 /IN T
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
P B 6
P B 7
P A 4
P A 5
P A 6
P A 7
O S C 2
O S C 1
V D D
R E S
P C 2
P C 0 /T M R
P A 3
P A 2
P A 1
P A 0
P B 3
P B 2
P B 1 /B Z
P B 0 /B Z
V S S
P G 0 /IN T
P C 0 /T M R
P C 1
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
P B 6
P B 7
P A 4
P A 5
P A 6
P A 7
O S C 2
O S C 1
V D D
R E S
P C 5
P C 4
P C 3
P C 2
HT48E30
H T 4 8 E 3 0
2 4 S K D IP -A /S O P -A
H T 4 8 E 3 0
2 8 S K D IP -A /S O P -A
Pad Assignment
P A 2
1
P A 3
3 1
P B 4
3 0
P B 5
2 9
P B 6
2 8
P B 7
2 7
P A 4
2 6
P A 5
2 5
T R IM 1
2
3
4
T R IM 2
T R IM 3
2 4
(0 ,0 )
P A 1
5
6
7
8
9
1 0
1 1
2 0
1 9
1 2
1 3
1 4
1 5
1 6
1 7
1 8
P A 0
P B 3
P B 2
P B 1 /B Z
P B 0 /B Z
V S S
2 3
2 2
2 1
P A 6
P A 7
O S C 2
O S C 1
V D D
R E S
P C 5
P C 4
P C 3
P C 2
P C 1
P G 0 /IN T
* The IC substrate should be connected to VSS in the PCB layout artwork.
P C 0 /T M R
Rev. 0.00
2
January 12, 2004
Preliminary
Pad Description
Pad Name
I/O
Options
Pull-high*
Wake-up
CMOS/Schmitt trigger
Input
Description
HT48E30
PA0~PA7
I/O
Bidirectional 8-bit input/output port. Each bit can be configured as a
wake-up input by options. Software instructions determine the CMOS
output or Schmitt trigger or CMOS input (depends on options) with
pull-high resistor (determined by 1-bit pull-high options).
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output or Schmitt trigger input with pull-high resistor (deter-
mined by pull-high options).
The PB0 and PB1 are pin-shared with the BZ and BZ, respectively.
Once the PB0 or PB1 is selected as buzzer driving outputs, the output
signals come from an internal PFD generator (shared with timer/event
counter).
Negative power supply, ground
Bidirectional I/O lines. Software instructions determine the CMOS out-
put or Schmitt trigger input with pull-high resistor (determined by 1-bit
pull-high options). This external interrupt input is pin-shared with PG0.
The external interrupt input is activated on a high to low transition.
Bidirectional I/O lines. Software instructions determine the CMOS out-
put or Schmitt trigger input with pull-high resistor (determined by 1-bit
pull-high options). The timer input are pin-shared with PC0.
Schmitt trigger reset input. Active low.
Positive power supply
OSC1and OSC2 are connected to an RC network or Crystal (deter-
mined by options) for the internal system clock. In the case of RC oper-
ation, OSC2 is the output terminal for 1/4 system clock.
PB0/BZ
PB1/BZ
PB2~PB7
I/O
Pull-high*
PB0 or BZ
PB1 or BZ
VSS
¾
¾
PG0/INT
I/O
Pull-high*
PC0/TMR
PC1~PC5
RES
VDD
OSC1
OSC2
Note:
I/O
I
¾
I
O
Pull-high*
¾
¾
Crystal or RC
²*²
The pull-high resistors of each I/O port (PA, PB, PC, PG) are controlled by a 1-bit option.
CMOS or Schmitt trigger option of port A is controlled by a 1-bit option.
Absolute Maximum Ratings
Supply Voltage ...........................V
SS
-0.3V
to V
SS
+6.0V
Input Voltage..............................V
SS
-0.3V
to V
DD
+0.3V
Storage Temperature ............................-50°C to 125°C
Operating Temperature...........................-40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under
²Absolute
Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
Rev. 0.00
3
January 12, 2004
Preliminary
D.C. Characteristics
Symbol
Parameter
Test Conditions
V
DD
¾
¾
3V
Operating Current (Crystal OSC)
5V
I
DD2
I
DD3
I
STB1
3V
Operating Current (RC OSC)
5V
Operating Current (Crystal OSC)
Standby Current (WDT Enabled)
5V
I
STB2
V
IL1
V
IH1
V
IL2
V
IH2
V
LVR
I
OL
3V
Standby Current (WDT Disabled)
5V
Input Low Voltage for I/O Ports
Input High Voltage for I/O Ports
Input Low Voltage (RES)
Input High Voltage (RES)
Low Voltage Reset Voltage
I/O Port Sink Current
¾
¾
¾
¾
¾
¾
¾
¾
¾
LVR enabled
No load, system HALT
5V No load, f
SYS
=8MHz
3V
No load, system HALT
No load, f
SYS
=4MHz
Conditions
f
SYS
=4MHz
f
SYS
=8MHz
No load, f
SYS
=4MHz
Min.
2.2
3.3
¾
¾
¾
¾
¾
¾
¾
¾
¾
0
0.7V
DD
0
0.9V
DD
2.7
4
10
-2
-5
40
10
Typ.
¾
¾
0.6
2
0.8
2.5
3
¾
¾
¾
¾
¾
¾
¾
¾
3.0
8
20
-4
-10
60
30
HT48E30
Ta=25°C
Max.
5.5
5.5
1.5
4
1.5
4
5
5
10
1
2
0.3V
DD
V
DD
0.4V
DD
V
DD
3.3
¾
¾
¾
¾
80
50
Unit
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
V
mA
mA
mA
mA
kW
kW
V
DD
Operating Voltage
I
DD1
3V V
OL
=0.1V
DD
5V V
OL
=0.1V
DD
I
OH
I/O Port Source Current
3V V
OH
=0.9V
DD
5V V
OH
=0.9V
DD
3V
R
PH
Pull-high Resistance
5V
¾
¾
Rev. 0.00
4
January 12, 2004
Preliminary
A.C. Characteristics
Symbol
Parameter
Test Conditions
V
DD
¾
¾
¾
¾
¾
¾
3V
5V
t
WDT1
t
WDT2
t
RES
t
SST
t
INT
3V
Watchdog Time-out Period (WDT OSC)
5V
Watchdog Time-out Period (System Clock)
External Reset Low Pulse Width
System Start-up Timer Period
Interrupt Pulse Width
¾
¾
¾
¾
Without WDT prescaler
¾
Wake-up from HALT
¾
Without WDT prescaler
8
¾
1
¾
1
17
1024
¾
1024
¾
Conditions
2.2V~5.5V
3.3V~5.5V
2.2V~5.5V
3.3V~5.5V
2.2V~5.5V
3.3V~5.5V
¾
¾
Min.
400
400
400
400
0
0
45
32
11
Typ.
¾
¾
¾
¾
¾
¾
90
65
23
HT48E30
Ta=25°C
Max.
4000
8000
4000
8000
4000
8000
180
130
46
33
¾
¾
¾
¾
Unit
kHz
kHz
kHz
kHz
kHz
kHz
ms
ms
ms
ms
t
SYS
ms
t
SYS
ms
f
SYS1
System Clock (Crystal OSC)
f
SYS2
System Clock (RC OSC)
f
TIMER
Timer I/P Frequency (TMR)
t
WDTOSC
Watchdog Oscillator Period
Rev. 0.00
5
January 12, 2004
PCB设计
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