Field Programmable SS VersaClock®
Synthesizer
ICS251
DATASHEET
Description
The ICS251 is a low cost, single-output, field programmable
clock synthesizer. The ICS251 can generate an output
frequency from 314kHz to 200MHz and may employ Spread
Spectrum techniques to reduce system electro-magnetic
interference (EMI).
Using IDT’s VersaClock software to configure the PLL and
output, the ICS251 contains a One-Time Programmable
(OTP) ROM to allow field programmability. Programming
features include 4 selectable configuration registers.
The device employs Phase-Locked Loop (PLL) techniques to
run from a standard fundamental mode, inexpensive crystal,
or clock. It can replace multiple crystals and oscillators,
saving board space and cost.
The device also has a power-down feature that tri-states the
clock outputs and turns off the PLLs when the PDTS pin is
taken low.
The ICS251 is also available in factory programmed custom
versions for high-volume applications.
Features
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8-pin SOIC package
Four addressable registers
Input crystal frequency of 5 to 27MHz
Clock input frequency of 3 to 150MHz
Output clock frequencies up to 200MHz
Configurable spread spectrum modulation
Operating voltage of 3.3V
Replaces multiple crystals and oscillators
Controllable output drive levels
Advanced, low-power CMOS process
RoHS compliant packaging
Block Diagram
VDD
S1:0
2
OTP ROM
with PLL
Divider
Values
Crystal or
clock input
X1/ICLK
Crystal
Oscillator
X2
External capacitors are
required with a crystal input.
PLL Clock Synthesis,
Spread Spectrum and
Control Circuitry
CLK
GND
PDTS (output and PLL)
ICS251 OCTOBER 10, 2017
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©2017 Integrated Device Technology, Inc.
ICS251 DATASHEET
Pin Assignment
S0
VDD
X1/ICLK
X2
1
2
3
4
8
7
6
5
PDTS
GND
S1
CLK
Output Clock Selection Table
S1
0
0
1
1
S0
0
1
0
1
CLK (MHz)
User Configurable
User Configurable
User Configurable
User Configurable
Spread
Percentage
User Configurable
User Configurable
User Configurable
User Configurable
8-pin (150 mil) SOIC
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
S0
VDD
X1/ICLK
X2
CLK
S1
GND
PDTS
Pin
Type
Input
Power
XI
XO
Output
Input
Power
Input
Connect to +3.3 V.
Pin Description
Select pin 0 for frequency selection on CLK. Internal pull-up resistor.
Connect this pin to a crystal or external clock input.
Connect this pin to a crystal, or float for clock input.
Clock output. Weak internal pull-down when tri-state.
Select pin 1 for frequency selection on CLK. Internal pull-up resistor.
Connect this to ground.
Powers down entire chip. Tri-states CLK outputs when low. No internal pull-up resistor. The pin must
be tied either directly or through the external resistor to VDD or GND. External resistor value must be
less than 15kOhm.
External Components
The ICS251 requires a minimum number of external
components for proper operation.
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep stray
capacitance to a minimum by using very short PCB traces
(and no vias) been the crystal and device. Crystal capacitors
must be connected from each of the pins X1 and X2 to ground.
The value (in pF) of these crystal caps should equal (C
L
-6pF)
× 2. In this equation, C
L
= crystal load capacitance in pF.
Example: For a crystal with a 16pF load capacitance, each
crystal capacitor would be 20pF [(16-6) x 2] = 20.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50 trace (a commonly
used trace impedance), place a 33 resistor in series with the
clock line, as close to the clock output pin as possible. The
nominal impedance of the clock output is 20.
Decoupling Capacitor
As with any high-performance mixed-signal IC, the ICS251
must be isolated from system power supply noise to perform
optimally.
A decoupling capacitor of 0.01µF must be connected between
VDD and the PCB ground plane.
Crystal Load Capacitors
The device crystal connections should include pads for small
capacitors from X1 to ground and from X2 to ground. These
capacitors are used to adjust the stray capacitance of the
board to match the nominally required crystal load
FIELD PROGRAMMABLE SS VERSACLOCK® SYNTHESIZER
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OCTOBER 10, 2017
ICS251 DATASHEET
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01µF decoupling capacitor should be mounted on the
component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitor and VDD pin. The PCB trace to VDD pin should be
kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) The external crystal should be mounted just next to the
device with short traces. The X1 and X2 traces should not be
routed next to each other with minimum spaces, instead they
should be separated and away from other traces.
3) To minimize EMI, the 33 series termination resistor (if
needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the same
side of the board, minimizing vias through other signal layers.
Other signal traces should be routed away from the ICS251.
This includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the device.
IDT VersaClock Software
IDT applies years of PLL optimization experience into a user
friendly software that accepts the user’s target reference clock
and output frequencies and generates the lowest jitter, lowest
power configuration, with only a press of a button. The user
does not need to have prior PLL experience or determine the
optimal VCO frequency to support multiple output
frequencies.
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and provides
an easy to understand, bar code rating for the target output
frequencies. The user may evaluate output accuracy,
performance trade-off scenarios in seconds.
Spread Spectrum Modulation
The ICS251 utilizes frequency modulation (FM) to distribute
energy over a range of frequencies. By modulating the output
clock frequencies, the device effectively lowers energy across
a broader range of frequencies; thus, lowering a system’s
electro-magnetic interference (EMI). The modulation rate is
the time from transitioning from a minimum frequency to a
maximum frequency and then back to the minimum.
Spread Spectrum Modulation can be applied as either “center
spread” or “down spread”. During center spread modulation,
the deviation from the target frequency is equal in the positive
and negative directions. The effective average frequency is
equal to the target frequency. In applications where the clock
is driving a component with a maximum frequency rating,
down spread should be applied. In this case, the maximum
frequency, including modulation, is the target frequency. The
effective average frequency is less than the target frequency.
The ICS251 operates in both center spread and down spread
modes. For center spread, the frequency can be modulated
between ±0.125% to ±2.0%. For down spread, the frequency
can be modulated between -0.25% to -4.0%.
Both output frequency banks will utilize identical spread
spectrum percentage deviations and modulation rates, if a
common VCO frequency can be identified.
ICS251 Configuration Capabilities
The architecture of the ICS251 allows the user to easily
configure the device to a wide range of output frequencies, for
a given input reference frequency.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be set
within the range of M = 1 to 2048 and N = 1 to 1024.
The ICS251 also provides separate output divide values, from
2 through 20, to allow the two output clock banks to support
widely differing frequency values from the same PLL.
Each output frequency can be represented
as:
OutputFreq
=
REFFreq
-------------------------------------
-
OutputDivide
----
-
M
N
Spread Spectrum Modulation Rate
The spread spectrum modulation frequency applied to the
output clock frequency may occur at a variety of rates. For
applications requiring the driving of “down-circuit” PLLs, Zero
Delay Buffers, or those adhering to PCI standards, the spread
spectrum modulation rate should be set to 30–33kHz. For
other applications, a 120kHz modulation option is available.
Output Drive Control
The ICS251 has two output drive settings. Low drive should
be selected when outputs are less than 100MHz. High drive
should be selected when outputs are greater than 100MHz.
(Consult the AC Electrical Characteristics for output rise and
fall times for each drive option.)
OCTOBER 10, 2017
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FIELD PROGRAMMABLE SS VERSACLOCK® SYNTHESIZER
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