IDT29FCT2052AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS
OCTAL REGISTERED
TRANSCEIVER
IDT29FCT2052AT/BT/CT
FEATURES:
−
−
−
−
−
−
−
−
Low input and output leakage
≤1µ
A (max.)
CMOS power levels
True TTL input and output compatibility
•
V
OH
= 3.3V (typ.)
•
V
OL
= 0.3V (typ.)
Meets or exceeds JEDEC standard 18 specifications
A, B and C speed grades
Resistor outputs
(-15mA I
OH
, 12mA I
OL
)
Reduced system switching noise
Available in SOIC and QSOP packages
DESCRIPTION:
The IDT29FCT2052T is an 8-bit registered transceiver built using an
advanced dual metal CMOS technology. Two 8-bit back-to-back registers
store data flowing in both directions between two bidirectional buses.
Separate clock, clock enable and 3-state output enable signals are provided
for each register. Both A outputs and B outputs are guaranteed to sink 64mA.
The IDT29FCT2052T has balanced drive outputs with current limiting
resistors. This offers low ground bounce, minimal undershoot and con-
trolled output fall times-reducing the need for external series terminating
resistors. The IDT29FCT2052T is a plug-in replacement for the IDT29FCT52T.
FUNCTIONAL BLOCK DIAGRAM
CPA
CEA
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
D
0
CE
D
1
D
2
D
3
D
4
D
5
D
6
D
7
A
Reg.
CP
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
OEB
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
CE
OEA
B
Reg.
D
0
D
1
D
2
D
3
D
4
D
5
D
6
CP D
7
CPB
CEB
INDSUTRIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
AUGUST 2000
DSC-5482/-
IDT29FCT2052AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
OEB
CPA
CEA
GND
1
2
3
4
5
6
7
8
9
10
11
12
SO24-2
SO24-8
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
OEA
CPB
CEB
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM(2)
V
TERM(3)
T
STG
I
OUT
Rating
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max.
–0.5 to +7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +120
Unit
V
V
°C
mA
8T-link
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. Inputs and Vcc terminals only.
3. Outputs and I/O terminals only.
CAPACITANCE
(T
A
= +25
O
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max.
10
12
Unit
pF
pF
8T-link
NOTE:
1. This parameter is measured at characterization but not tested.
SOIC/ QSOP
TOP VIEW
REGISTER FUNCTION TABLE
(1)
(Applies to A or B Register)
D
X
L
H
Inputs
CP
X
↑
↑
CE
H
L
L
Internal
Q
NC
L
H
Function
Hold Data
Load Data
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
NC = No Change
↑
= LOW-to-HIGH Transition
OUTPUT CONTROL
(1)
Internal
OE
H
L
L
Q
X
L
H
Y-Outputs
Z
L
H
Function
Disable Outputs
Enable Outputs
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
2
IDT29FCT2052AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Name
A
0-7
B
0-7
CPA
CEA
OEB
CPB
CEB
OEA
I/O
I/O
I/O
I
I
I
I
I
I
Description
Eight bidirectional lines carrying the A Register inputs or B Register outputs.
Eight bidirectional lines carrying the B Register inputs or A Register outputs.
Clock for the A Register. When
CEA
is LOW, data is entered into the A Register on the LOW-to-HIGH transition of the CPA signal.
Clock Enable for the A Register. When
CEA
is LOW, data is entered into the A Register on the LOW-to-HIGH transition of the CPA signal. When
CEA
is HIGH, the A Register holds its contents, regardless of CPA signal transitions.
Output Enable for the A Register. When
OEB
is LOW, the A Register outputs are enabled onto the B
0-7
lines. When
OEB
is HIGH, the B
0-7
outputs
are in the high-impedance state.
Clock for the B Register. When
CEB
is LOW, data is entered into the B Register on the LOW-to-HIGH transition of the CPB signal.
Clock Enable for the B Register. When
CEB
is LOW, data is entered into the B Register on the LOW-to-HIGH transition of the CPB signal. When
CEB
is HIGH, the B Register holds its contents, regardless of CPB signal transitions.
Output Enable for the B Register. When
OEA
is LOW, the B Register outputs are enabled onto the A
0-7
lines. When
OEA
is HIGH, the A
0-7
outputs
are in the high-impedance state.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= -40°C to +85°C, V
CC
= 5.0V ± 5%
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
I
V
IK
V
H
I
CC
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(4)
Input LOW Current
(4)
High Impedance Output Current
(3-State Output pins)
(4)
Input HIGH Current
(4)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Max., V
I
= V
CC
(Max.)
V
CC
= Min., I
IN
= –18mA
—
V
CC
= 3V, V
IN
= GND or V
CC
V
CC
= Max.
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= 2.7V
V
I
= 0.5V
V
O
= 2.7V
V
O
= 0.5V
Min.
2
—
—
—
—
—
—
—
—
—
Typ.
(2)
—
—
—
—
—
—
—
–0.7
200
0.01
Max.
—
0.8
±1
±1
±1
±1
±1
–1.2
—
1
µA
V
mV
mA
Unit
V
V
µA
OUTPUT DRIVE CHARACTERISTICS
Symbol
I
ODL
I
ODH
V
OH
V
OL
Parameter
Output LOW Current
Output HIGH Current
Output HIGH Voltage
Output LOW Voltage
Test Conditions
(1)
V
CC
= 5V, V
IN
= V
IH
or V
IL,
V
OUT
= 1.5V
(3)
V
CC
= 5V, V
IN
= V
IH
or V
IL,
V
OUT
= 1.5V
(3)
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= Min.
V
IN
= V
IH
or V
IL
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is ±5µA at T
A
= -55°C.
Min.
16
–16
2.4
—
Typ.
(2)
48
–48
3.3
0.3
Max.
—
—
—
0.5
Unit
mA
mA
V
V
I
OH
= -15mA
I
OL
= 12mA
3
IDT29FCT2052AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current
(4)
Test Conditions
(1)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
OE
A
or
OE
B
= GND
One Input Toggling
50% Duty Cycle
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
OE
A
or
OE
B
= GND
One Bit Toggling
at fi = 5MHz
50% Duty Cycle
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
OE
A
or
OE
B
= GND
Eight Bits Toggling
at fi = 2.5MHz
50% Duty Cycle
Min.
—
—
Typ.
(2)
0.5
0.06
Max.
2
0.12
Unit
mA
mA/
MHz
V
IN
= V
CC
V
IN
= GND
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
—
0.6
2.2
mA
V
IN
= 3.4V
V
IN
= GND
—
1.1
4.2
V
IN
= V
CC
V
IN
= GND
—
1.5
4
(5)
V
IN
= 3.4V
V
IN
= GND
—
3.8
13
(
5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP/
2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
4
IDT29FCT2052AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
29FCT2052AT
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
SU
t
H
t
W
Parameter
Propagation Delay
CPA, CPB to An, Bn
Output Enable Time
OEA
or
OEB
to An, Bn
Output Disable Time
OEA
or
OEB
to An, Bn
Set-up Time, HIGH or LOW
An, Bn to CPA, CPB
Hold Time, HIGH or LOW
An, Bn to CPA, CPB
Set-up Time, HIGH or LOW
CEA
,
CEB
to CPA, CPB
Hold Time, HIGH or LOW
CEA
,
CEB
to CPA, CPB
Clock Pulse Width HIGH or LOW
(3)
Condition
(1)
C
L
= 50pF
R
L
= 500Ω
Min
.
(2)
2
1.5
1.5
2.5
2
3
2
3
Max.
10
10.5
10
—
—
—
—
—
29FCT2052BT
Min
.
(2)
2
1.5
1.5
2.5
1.5
3
2
3
Max.
7.5
8
7.5
—
—
—
—
—
(1)
29FCT2052CT
Min
.
(2)
2
1.5
1.5
2.5
1.5
3
2
3
Max.
6.3
7
6.5
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
5
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