2M x 32
CMOS Static RAM Module
PRELIMINARY
IDT7MPV4130
Features
x
x
x
x
x
x
x
High-density 8MB Static RAM module
72-pin SIMM (Single In-line Memory Module)
Fast access time: 15ns (max.)
Surface mounted plastic components on an epoxy
laminate (FR-4) substrate
Single 3.3V (±10%) power supply
Multiple GND pins and decoupling capacitors for maximum
noise immunity
Inputs/outputs directly LVTTL-compatible
Description
The IDT7MPV4130 is a 2M x 32 Static RAM module constructed on
an epoxy laminate (FR-4) substrate using 16 1M x 4 Static RAMs in plastic
packages as well as on board buffering and decoding. Availability of four
chip select lines (one for each group of four RAMs) provides byte access.
The IDT7MPV4130 is available with access time as fast as 15ns with
minimal power consumption.
The IDT7MPV4130 is packaged in•a 72-pin SIMM (Single In-line
Memory Module). The SIMM configuration allows use of edge mounted
sockets to secure the module.
All inputs and outputs of the IDT7MPV4130 are LVTTL-compatible and
operate from a single 3.3V supply. Full asynchronous circuitry requires
no clocks or refresh for operation and provides equal access and cycle
times for ease of use.
Four identification pins (PD
0
, PD
1
, PD
2
and PD
3
) are provided for
applications in which different density versions of the module are used. In
this way, the target system can read the respective levels of PD
0
, PD
1
, PD
2
and PD
3
to determine a 2M depth.
The contact pins are plated with 100 micro-inches of nickel covered
by 30 micro-inches minimum of selective gold.
Pin Configuration
(1)
NC
PD
3
PD
0
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
A
7
A
8
A
9
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
14
CS
1
CS
3
A
16
GND
I/O
16
I/O
17
I/O
18
I/O
19
A
10
A
11
A
12
A
13
I/O
20
I/O
21
I/O
22
I/O
23
GND
A
19
NC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
NC
PD
2
GND
PD
1
I/O
8
I/O
9
I/O
10
I/O
11
A
0
A
1
A
2
I/O
12
I/O
13
I/O
14
I/O
15
GND
A
15
CS
2
CS
4
A
17
OE
I/O
24
I/O
25
I/O
26
I/O
27
A
3
A
4
A
5
V
CC
A
6
I/O
28
I/O
29
I/O
30
I/O
31
A
18
A
20
4273 drw 01
PD
0 -
NC
PD
1 -
GND
PD
2 -
GND
PD
3 -
NC
,
Pin Names
I/O
0
- I/O
31
A
0
- A
20
CS
1
-
CS
4
WE
OE
PD
0
- PD
3
V
CC
GND
NC
Data Inputs/Outputs
Addresses
Chip Selects
Write Enable
Output Enable
Depth Identification
Power
Ground
No Connect
4273 tbl 01
NOTE:
1. Pins 3 (PD
2
), 4 (PD
3
), 6 (PD
0
) and 7 (PD
1
) are read by the user to determine
the density of the module. If PD
0
reads NC, PD
1
reads GND, PD
2
reads GND
and PD
3
reads NC, then the module has a 2M depth.
SIMM
Top View
JANUARY 2000
1
©2000 Integrated Device Technology, Inc.
DSC-4273/2
IDT7MPV4130
2M x 32 CMOS Static RAM Module
Preliminary
Commercial Temperature Ranges
Functional Block Diagram
7MPV4130
A
20
4
Present Detect Table
Module
7MPV4130
PD
0
Open
PD
1
GND
PD
2
GND
PD
3
Open
4273 tbl 02
CS
1
-
CS
4
DECODER
PD
0
- PD
3
A
0
-A
19
20
Capacitance
(T
)
= +25°C, f = 1.0MHz)
Symbo
Parameter
I/O Capacitance
Input Capacitance
(Address)
Input Capacitance
(WE,
OE)
Input Capacitance
(CS)
Condition
V
I/O
= 0V
V
IN
= 0V
V
IN
= 0V
V
IN
= 0V
Max.
20
10
10
10
Unit
pF
pF
pF
pF
3273 tbl 03
,
WE
OE
2M x 32
RAM
C
I/O
C
IN1
C
IN2
8
8
8
8
C
IN3
4273 drw 02
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
NOTE:
1. This parameter is guaranteed by design but not tested.
DC Electrical Characteristics
(V
++
= 3.3V ±10%, T
)
= 0°C to +70°C)
Symbo
II
LI
I
II
LI
I
II
LO
I
V
OL
V
OH
Parameter
Input Leakage Current
(Address and Control)
Input Leakage Current (Data)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Condit
V
CC
= Max., V
IN
= GND to V
CC
V
CC
= Max., V
IN
= GND to V
CC
V
CC
= Max.,
CS
= V
IH
, V
OUT
= GN
I
OL
= 8mA, V
CC
= Min.
I
OH
= -4mA, V
CC
= Min.
DC Electrical Characteristics
(V
++
= 3.3V ±10%, T
)
= 0°C to +70°C)
Symbo
I
CC
I
SB
I
SB1
Parameter
Dynamic Operating
Current
Standby Supply
Current
Full Standby
Supply Current
Test Condit
V
CC
= Max.,
CS
= V
IL
,
f = f
MAX
, Outputs Open
V
CC
= Max.,
CS
> V
IH
,
f = f
MAX
, Outputs Open
CS
> V
CC
- 0.2V, f =0,
V
IN
> V
CC
-0.2V or < 0.2V
2
IDT7MPV4130
2M x 32 CMOS Static RAM Module
Preliminary
Commercial Temperature Ranges
Recommended DC Operating
Conditions
Symbo
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
3.0
0
2.2
-0.5
(1)
Typ.
3.3
0
____
Truth Table
Mode
Unit
V
V
V
V
4273 tbl 06
CS
H
L
L
L
OE
X
L
X
H
WE
X
H
L
H
I/O
High-Z
DATA
OUT
DATA
IN
High-Z
Power
Standby
Active
Active
Active
4273 tbl 08
Max.
3.5
0
V
CC
+ 0.5
0.8
Standby
Read
Write
Outputs Disabled
____
NOTE:
1. V
il
(min) = –1.5V for pulse width less than 10ns.
Absolute Maximum Ratings
(1)
Recommended Operating
Temperature and Supply Voltage
Grade
Commercial
Ambient
Temperature
0°C to +70°C
GND
0V
V
CC
See Above
4273 tbl 07
Symbol
V
TERM
T
A
T
BIAS
T
STG
I
OUT
Rating
Terminal Voltage with Respect
to GND
Operating Temperature
Temperature Under Bias
Storage Temperature
DC Output Current
Rating
-0.5 to +4.6
0 to +70
-10 to +85
-55 to +125
50
Unit
V
°C
°C
°C
mA
4273 tbl 09
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
4273 tbl 10
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
+3.3 V
+3.3 V
320Ω
DATA
OUT
DATA
OUT
320Ω
350Ω
30 pF*
,
350Ω
5 pF*
,
4273 drw 03
4273 drw 04
Figure 1. Output Load
*Includes scope and jig.
Figure 2. Output Load
(for t
OLZ
,t
OHZ
, t
CHZ
, t
CLZ
, t
WHZ
, t
OW
)
6.42
3
IDT7MPV4130
2M x 32 CMOS Static RAM Module
Preliminary
Commercial Temperature Ranges
AC Electrical Characteristics
(V
++
= 3.3V ± .3V, T
)
= 0°C to +70°C)
Symbo
Parameter
M
Read Cycle
t
RC
t
AA
t
ACS
t
CLZ
(1)
t
OE
t
OLZ
(1)
t
CHZ
(1)
t
OHZ
(1)
t
OH
t
PU
(1)
t
PD
(1)
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select to Output in Low-Z
Output Enable to Output Vali
Output Enable to Output in Low-Z
Chip Deselect to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power-Up Time
Chip Deselect to Power-Down Time
Write Cycle
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
Write Cycle Time
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
NOTE:
1. This parameter is guaranteed by design, but not tested.
4
IDT7MPV4130
2M x 32 CMOS Static RAM Module
Preliminary
Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1
(1)
t
RC
ADDRESS
t
AA
OE
t
OE
CS
t
ACS
t
CLZ (5)
DATAOUT
t
OLZ (5)
Timing Waveform of Read Cycle No. 2
(1,2,4)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
PREVIOUS DATA VALID
Timing Waveform of Read Cycle No. 3
(1,3,4)
CS
t
ACS
t
CLZ
DATA
OUT
(5)
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Device is continuously selected.
CS
= V
IL
.
3. Address valid prior to or coincident with
CS
transition LOW.
4.
OE
= V
IL
.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.
6.42
5
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