2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM
Features
DDR2 SDRAM Mini-RDIMM
MT18HTS25672(P)K – 2GB
MT18HTS51272(P)K – 4GB
For component data sheets, refer to Micron’s Web site:
www.micron.com
Features
• 244-pin, mini registered dual in-line memory
module (Mini-RDIMM)
• Fast data transfer rates: PC2-3200, PC2-4200, or
PC2-5300
• Supports ECC error detection and correction
• 2GB (512 Meg x 72) and 4GB (1,024 Meg x 72)
• V
DD
= V
DD
Q = +1.8V
• V
DDSPD
= +1.7V to +3.6V
• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• 4n-bit prefetch architecture
• Multiple internal device banks for concurrent
operation
• Supports redundant output strobe (RDQS/RDQS#)
• Programmable CAS latency (CL)
• Posted CAS additive latency (AL)
• WRITE latency = READ latency - 1
t
CK
• Programmable burst length (BL) 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts
• Dual rank, TwinDie
TM
(2COB) DRAM devices
• Phase-lock loop (PLL) to reduce loading on system
clock
Figure 1:
244-Pin Mini-RDIMM (MO-244)
PCB height 30.0mm (1.18in
)
Options
• Parity
• Operating temperature
1
–
Commercial (0°C
≤
T
A
≤
+70°C)
–
Industrial (–40°C
≤
T
A
≤
+85°C)
• Package
–
244-pin DIMM (Pb-free)
• Frequency/CAS latency
2
–
3.0ns @ CL = 5 (DDR2-667)
–
3.75ns @ CL = 4 (DDR2-533)
Marking
P
None
I
Y
-667
-53E
Notes: 1. Contact Micron for industrial temperature
module offerings.
2. CL = CAS (READ) latency; registered mode
will add one clock cycle to CL.
Table 1:
Key Timing Parameters
Data Rate (MT/s)
t
Speed Grade
-667
-53E
CL = 5
667
–
CL = 4
533
533
CL = 3
400
400
RCD
(ns)
15
15
RP
(ns)
15
15
t
t
RC
(ns)
55
55
PDF: 09005aef82218d23/Source: 09005aef82218d00
HTS18C256_512x72K.fm - Rev. B 9/07 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM
Features
Table 2:
Parameter
Refresh count
Row address
Device bank address
Device page size per bank
TwinDie device configuration
Column address
Module rank address
Address Table
2GB
8K
16K (A0–A13)
8 (BA0– BA2)
1KB
2Gb TwinDie (256 Meg x 8)
1K (A0–A9)
2 (S0#, S1#)
4GB
8K
32K (A0–A14)
8 (BA0–BA2)
1KB
4Gb TwinDie (512 Meg x 8)
1K (A0–A9)
2 (S0#, S1#)
Table 3:
Part Numbers and Timing Parameters – 2GB Modules
Base Device: MT47H256M8THN,
1
2Gb TwinDie DDR2 SDRAM
Module
Density
2GB
2GB
Module
Bandwidth
5.3 GB/s
4.3 GB/s
Memory Clock/
Data Rate
3.0ns/667 MT/s
3.75ns/533 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
5-5-5
4-4-4
Part Number
2
MT18HTS25672(P)KY-667__
MT18HTS25672(P)KY-53E__
Configuration
256 Meg x 72
256 Meg x 72
Table 4:
Part Numbers and Timing Parameters – 4GB Modules
Base Device: MT47H512M8THM,
1
4Gb TwinDie DDR2 SDRAM
Module
Density
4GB
4GB
Module
Bandwidth
5.3 GB/s
4.3 GB/s
Memory Clock/
Data Rate
3.0ns/667 MT/s
3.75ns/533 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
5-5-5
4-4-4
Part Number
2
MT18HTS51272(P)KY-667__
MT18HTS51272(P)KY-53E__
Notes:
Configuration
512 Meg x 72
512 Meg x 72
1. Data sheets for the base devices can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and
PCB revisions. Consult factory for current revision codes. Example: MT18HTS25672PKY-
667E1.
PDF: 09005aef82218d23/Source: 09005aef82218d00
HTS18C256_512x72K.fm - Rev. B 9/07 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 5:
Pin Assignments
244-Pin Mini-RDIMM Front
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
NC
NC
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
V
SS
DQ18
DQ19
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
V
SS
DQ24
DQ25
V
SS
DQS3#
DQS3
V
SS
DQ26
DQ27
V
SS
CB0
CB1
V
SS
DQS8#
DQS8
V
SS
CB2
CB3
V
SS
NC
V
DD
Q
CKE0
V
DD
BA2
NU/
E
RR
_O
UT
V
DD
Q
A11
A7
V
DD
A5
A4
Notes:
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
V
DD
Q
A2
V
DD
V
SS
V
SS
NU/
P
AR
_I
N
V
DD
A10
BA0
V
DD
WE#
V
DD
Q
CAS#
V
DD
Q
S1#
ODT1
V
DD
Q
NC
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
V
SS
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
DQS5#
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
SA2
NC
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7#
DQS7
V
SS
DQ58
DQ59
V
SS
SA0
SA1
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
V
SS
DQ4
DQ5
V
SS
DM0/
RDQS0
NU/
RDQS0#
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1/
RDQS1
NU/
RDQS1#
V
SS
NC
NC
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2/
RDQS2
NU/
RDQS2#
V
SS
DQ22
DQ23
V
SS
244-Pin Mini-RDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
154
155
156
157
DQ28
185
186
187
188
189
190
191
192
193
194
195
196
A3
A1
V
DD
CK0
CK0#
V
DD
A0
BA1
V
DD
RAS#
V
DD
Q
S0#
V
DD
Q
ODT0
A13
V
DD
NC
V
SS
DQ36
DQ37
V
SS
NU/
RDQS5#
217
V
SS
218 DQ46
219 DQ47
220
221
222
223
224
225
226
227
V
SS
DQ52
216
DQ29
V
SS
DM3/
RDQS3
158
NU/
RDQS3#
159
V
SS
DQ30
DQ31
V
SS
CB4
CB5
V
SS
160
161
162
163
164
165
166
DM8/
197
RDQS8
167
NU/
198
RDQS8#
168
V
SS
199
169
170
171
172
173
174
175
CB6
CB7
V
SS
NC
V
DD
Q
CKE1
V
DD
200
201
202
203
204
205
206
DQ53
V
SS
RFU
RFU
V
SS
DM6/
RDQS6
228
NU/
RDQS6#
229
V
SS
230
DQ54
231
232
233
234
235
236
176
1
NU/A15
177
2
NU/A14
178
V
DD
Q
179
180
181
182
183
184
A12
A9
V
DD
A8
A6
V
DD
Q
DM4/
RDQS4
207
NU/
RDQS4#
208
V
SS
239
209 DQ38 240
210
211
212
213
214
215
DQ39
V
SS
DQ44
DQ45
V
SS
DM5/
RDQS5
241
242
DQ55
V
SS
DQ60
DQ61
V
SS
DM7/
RDQS7
237
NU/
RDQS7#
238
V
SS
DQ62
DQ63
V
SS
SDA
SCL
V
DDSPD
243
244
1. Pin 176 is NU for non-parity and A15 for parity.
2. Pin 177 is NU for 2GB and A14 for 4GB.
PDF: 09005aef82218d23/Source: 09005aef82218d00
HTS18C256_512x72K.fm - Rev. B 9/07 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM
Pin Assignments and Descriptions
Table 6:
Symbol
A0–A15
Pin Descriptions
Type
Input
(SSTL_18)
Description
Address inputs:
Provide the row address for ACTIVE commands, and the column address
and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA0–BA2) or all device banks (A10 HIGH). The address inputs also provide the op-
code during a LOAD MODE command. A0–A13 (2GB) and A0–A14 (4GB). A0–A15 are
connected for parity.
Bank address inputs:
BA0–BA2 define to which device bank an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA0–BA2 define which mode register, including MR,
EMR, EMR (2), and EMR (3), is loaded during the LOAD MODE command.
Clock:
CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output
data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock enable:
CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking
circuitry on the DDR2 SDRAM.
On-Die termination:
ODT (registered HIGH) enables termination resistance internal to the
DDR2 SDRAM. When enabled, ODT is only applied to each of the following pins: DQ, DQS,
DQS#, RDQS, RDQS#, CB, and DM. The ODT input will be ignored if disabled via the LOAD
MODE command.
Parity bit for the address and control bus. Non-parity version is not used.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Chip select:
S# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when S# is registered HIGH. S# provides for external rank
selection on systems with multiple ranks. S# is considered part of the command code.
Presence-detect address inputs:
These pins are used to configure the presence-detect
device.
Serial clock for presence-detect:
SCL is used to synchronize the presence-detect data
transfer to and from the module.
Data input/output:
Bidirectional data bus.
Data strobe:
Output with read data, input with write data for source synchronous
operation. Edge-aligned with read data, center-aligned with write data. DQS# is only used
when differential data strobe mode is enabled via the LOAD MODE command.
Check bits.
Data input mask:
DM is an input mask signal for write data. Input data is masked when DM
is sampled HIGH, along with that input data, during a write access. DM is sampled on both
edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of
DQ and DQS pins. If RDQS is disabled, DQS9–DQS17 become DM0–DM8 and DQS9#–DQS17#
are not used.
Serial presence-detect data:
SDA is a bidirectional pin used to transfer addresses and data
into and out of the presence-detect portion of the module.
Parity error found on the address and control bus. Non-parity version is not used.
Power supply:
1.8V ±0.1V.
DQ power supply:
1.8V ±0.1V.
Serial EEPROM positive power supply:
+1.7V to +3.6V.
SSTL_18 reference voltage (V
DD
/2).
BA0–BA2
Input
(SSTL_18)
Input
(SSTL_18)
Input
(SSTL_18)
Input
(SSTL_18)
CK0, CK0#
CKE0, CKE1
ODT0, ODT1
P
AR
_I
N
RAS#, CAS#,
WE#
S0#, S1#
Input
(SSTL_18)
Input
(SSTL_18)
Input
(SSTL_18)
Input
(SSTL_18)
Input
(SSTL_18)
I/O
(SSTL_18)
I/O
(SSTL_18)
I/O
(SSTL_18)
I/O
(SSTL_18)
SA0–SA2
SCL
DQ0–DQ63
DQS0–DQS8
CB0–CB7
DM0–DM8/
RDQS0–RDQS8
SDA
E
RR
_O
UT
V
DD
V
DD
Q
V
DDSPD
V
REF
I/O
(SSTL_18)
Output
(open drain)
Supply
Supply
Supply
Supply
PDF: 09005aef82218d23/Source: 09005aef82218d00
HTS18C256_512x72K.fm - Rev. B 9/07 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM
Pin Assignments and Descriptions
Table 6:
Symbol
V
SS
NC
NU
RFU
Pin Descriptions (continued)
Type
Supply
–
–
–
Description
Ground.
No connect:
These pins are not connected on the module.
Not used:
These pins are not required to be used.
Reserved for future use.
PDF: 09005aef82218d23/Source: 09005aef82218d00
HTS18C256_512x72K.fm - Rev. B 9/07 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
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