Preliminary
HY27UA(08/16)1G1M Series
HY27SA(08/16)1G1M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Document Title
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory
Revision History
No.
0.0
0.1
1) Initial Draft
1) Add 1.8V Operation Product to Data sheet
1) Change AC Characteristics
0.2
- tWP(25ns->40ns), tWC(50ns->60ns),
- tRP(30ns->40ns), tRC(50ns->60ns),
- tREADID(35ns->45ns)
1) Add Errata (3V Product)
tWH
Specification
Relaxed value
0.3
2) Add Applicaiton Note
Reset command must be issued when the controller writes data to
another 512Mb.(i.e. When A26 is changed during program.)
3) Modify the description of Device Operations
- /CE Don’t Care Enabled(Disabled) -> Sequential Row Read Disabled
(Enabled) (Page23)
4) Add the description of System Interface Using /CE don’t care (Page40)
15
20
tREH
15
20
May. 14. 2004
Preliminary
Apr. 29. 2004
Preliminary
History
Draft Date
Nov. 28. 2003
Mar. 11. 2004
Remark
Preliminary
Preliminary
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.3 / May. 2004
1
Preliminary
HY27UA(08/16)1G1M Series
HY27SA(08/16)1G1M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
- Cost effective solutions for mass storage applications
FAST BLOCK ERASE
- Block erase time: 2ms (Typ)
NAND INTERFACE
- x8 or x16 bus width.
- Multiplexed Address/ Data
- Pinout compatibility for all densities
STATUS REGISTER
ELECTRONIC SIGNATURE
SUPPLY VOLTAGE
CHIP ENABLE DON'T CARE OPTION
: HY27UAXX1G1M
- Simple interface with microcontroller
- 3.3V device: VCC = 2.7 to 3.6V
1.8V Operation Product : TBD
- 1.8V device: VCC = 1.7 to 1.95V : HY27SAXX1G1M
AUTOMATIC PAGE 0 READ AT POWER-UP
OPTION
- Boot from NAND support
- Automatic Memory Download
Memory Cell Array
- 1056Mbit = 528 Bytes x 32 Pages x 8,192 Blocks
SERIAL NUMBER OPTION
HARDWARE DATA PROTECTION
- Program/Erase locked during Power transitions
PAGE SIZE
- x8 device: (512 + 16 spare) Bytes
: HY27(U/S)A081G1M
- x16 device: (256 + 8 spare) Words
: HY27(U/S)A161G1M
DATA INTEGRITY
- 100,000 Program/Erase cycles
- 10 years Data Retention
BLOCK SIZE
- x8 device: (16K + 512 spare) Bytes
: HY27(U/S)A081G1M
- x16 device: (8K + 256 spare) Words
: HY27(U/S)A161G1M
PACKAGE
- HY27(U/S)A(08/16)1G1M-T(P)
: 48-Pin TSOP1 (12 x 20 x 1.2 mm)
- HY27(U/S)A(08/16)1G1M-T (Lead)
- HY27(U/S)A(08/16)1G1M-TP (Lead Free)
- HY27(U/S)A08121A-V(P)
: 48-Pin WSOP1 (12 x 17 x 0.7 mm)
- HY27(U/S)A081G1M-V (Lead)
- HY27(U/S)A081G1M-VP (Lead Free)
- HY27(U/S)A(08/16)121M-F(P)
: 63-Ball FBGA (8.5 x 15 x 1.2 mm)
- HY27(U/S)A(08/16)1G1M-F (Lead)
- HY27(U/S)A(08/16)1G1M-FP (Lead Free)
PAGE READ / PROGRAM
- Random access: 12us (max)
- Sequential access: 50ns (min)
- Page program time: 200us (typ)
COPY BACK PROGRAM MODE
- Fast page copy without external buffering
CACHE PROGRAM MODE
- Internal Cache Register to improve the program
throughput
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.3 / May. 2004
2
Preliminary
HY27UA(08/16)1G1M Series
HY27SA(08/16)1G1M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
DESCRIPTION
The HYNIX HY27(U/S)A(08/16)1G1M series is a family of non-volatile Flash memories that use NAND cell technology.
The devices operate 3.3V and 1.8V voltage supply. The size of a Page is either 528 Bytes (512 + 16 spare) or 264
Words (256 + 8 spare) depending on whether the device has a x8 or x16 bus width.
The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x8 or x16 Input/ Output bus.
This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint.
Each block can be programmed and erased over 100,000 cycles. To extend the lifetime of NAND Flash devices it is
strongly recommended to implement an Error Correction Code (ECC). A Write Protect pin is available to give a hard-
ware protection against program and erase operations.
The devices feature an open-drain Ready/Busy output that can be used to identify if the Program/ Erase/Read (PER)
Controller is currently active. The use of an open-drain output allows the Ready/ Busy pins from several memories to
be connected to a single pull-up resistor.
A Copy Back command is available to optimize the management of defective blocks. When a Page Program operation
fails, the data can be programmed in another page without having to resend the data to be programmed.
Each device has a Cache Program feature which improves the program throughput for large files. It loads the data in a
Cache Register while the previous data is transferred to the Page Buffer and programmed into the memory array.
The devices are available in the following packages:
-
48-TSOP1
(12 x 20 x 1.2 mm)
- 48-WSOP1
(12 x 17 x 0.7 mm)
- 63-FBGA
(8.5 x 15 x 1.2 mm, 6 x 8 ball array, 0.8mm pitch)
Three options are available for the NAND Flash family:
- Automatic Page 0 Read after Power-up, which allows the microcontroller to directly download the boot code from
page 0.
- Chip Enable Dont Care, which allows code to be directly downloaded by a microcontroller, as Chip Enable transitions
during the latency time do not stop the read operation.
- A Serial Number, which allows each device to be uniquely identified. The Serial Number options is subject to an NDA
(Non Disclosure Agreement) and so not described in the datasheet. For more details of this option contact your near-
est HYNIX Sales office.
Devices are shipped from the factory with Block 0 always valid and the memory content bits, in valid blocks, erased to
'1'.
Rev 0.3 / May. 2004
3
Preliminary
HY27UA(08/16)1G1M Series
HY27SA(08/16)1G1M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Vcc
I/O
8-15
I/O
0-7
I/O8-I/O15, x16
Data Input/Outputs for x16 Device
Data Input/Output, Address Inputs, or Com-
mand Inputs for x8 and x16 device
Address Latch Enable
Command Latch Enable
Chip Enable
Read Enable
Read/Busy (open-drain output)
Write Enable
Write Protect
Supply Voltage
Ground
Not Connected Internally
Do Not Use
CE
RE
WE
ALE
CLE
WP
I/O0-I/O7, x8/x16
ALE
CLE
CE
NAND
Flash
RB
RE
RB
WE
WP
VCC
Vss
VSS
NC
DU
Figure 1: Logic Diagram
Table 1: Signal Name
Address
Register/Counter
ALE
CLE
WE
CE
WP
RE
Command Register
Command
Interface
Logic
P/E/R
Controller,
High Voltage
Generator
X Decoder
NAND Flash
Memory Array
Page Buffer
Cache Register
Y Decoder
I/O Buffers &
Latches
RB
I/O0-I/O7, x8/x16
I/O8-I/O15, x16
Figure 2. LOGIC BLOCK DIAGRAM
Rev 0.3 / May. 2004
4
Preliminary
HY27UA(08/16)1G1M Series
HY27SA(08/16)1G1M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
NC
NC
NC
NC
NC
NC
RB
RE
CE
NC
NC
Vcc
Vss
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
1
48
12
13
NAND Flash
(x8)
37
36
24
25
NC
NC
NC
NC
I/O 7
I/O 6
I/O 5
I/O 4
NC
NC
NC
Vcc
Vss
NC
NC
NC
I/O 3
I/O 2
I/O 1
I/O 0
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
RB
RE
CE
NC
NC
Vcc
Vss
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
1
48
12
13
NAND Flash
(x16)
37
36
24
25
Vss
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
NC
NC
Vcc
NC
NC
NC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
Vss
Figure 3. 48-TSOP1 Contactions, x8(x16) Device
NC
NC
DU
NC
NC
NC
RB
RE
CE
DU
NC
Vcc
Vss
NC
DU
CLE
ALE
WE
WP
NC
NC
DU
NC
NC
1
48
NAND Flash
WSOP1
37
12
36
13
(x8)
24
25
NC
NC
DU
NC
I/O7
I/O6
I/O5
I/O4
NC
DU
NC
Vcc
Vss
NC
DU
NC
I/O3
I/O2
I/O1
I/O0
NC
DU
NC
NC
Figure 4. 48-WSOP1 Contactions, x8 Device
Rev 0.3 / May. 2004
5
FPGA/CPLD
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